Area-power-delay trade-off in logic synthesis:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
1992
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| Schlagworte: | |
| Beschreibung: | Eindhoven, Techn. Univ., Diss., 1992 |
| Beschreibung: | XVII, 117 S. graph. Darst. |
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Datensatz im Suchindex
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|---|---|
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| author | Berkelaar, Michel R. |
| author_facet | Berkelaar, Michel R. |
| author_role | aut |
| author_sort | Berkelaar, Michel R. |
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| building | Verbundindex |
| bvnumber | BV008381229 |
| classification_tum | ELT 273d |
| ctrlnum | (OCoLC)55851260 (DE-599)BVBBV008381229 |
| discipline | Elektrotechnik |
| format | Book |
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| id | DE-604.BV008381229 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:18:59Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-005526792 |
| oclc_num | 55851260 |
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| owner_facet | DE-91 DE-BY-TUM |
| physical | XVII, 117 S. graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| record_format | marc |
| spelling | Berkelaar, Michel R. Verfasser aut Area-power-delay trade-off in logic synthesis door Michel R.C.M. Berkelaar 1992 XVII, 117 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Eindhoven, Techn. Univ., Diss., 1992 Computermethoden gtt Logica gtt Ontwerpen gtt VLSI gtt Logik Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Logischer Entwurf (DE-588)4168051-0 s Integrierte Schaltung (DE-588)4027242-4 s DE-604 |
| spellingShingle | Berkelaar, Michel R. Area-power-delay trade-off in logic synthesis Computermethoden gtt Logica gtt Ontwerpen gtt VLSI gtt Logik Logischer Entwurf (DE-588)4168051-0 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4168051-0 (DE-588)4027242-4 (DE-588)4113937-9 |
| title | Area-power-delay trade-off in logic synthesis |
| title_auth | Area-power-delay trade-off in logic synthesis |
| title_exact_search | Area-power-delay trade-off in logic synthesis |
| title_full | Area-power-delay trade-off in logic synthesis door Michel R.C.M. Berkelaar |
| title_fullStr | Area-power-delay trade-off in logic synthesis door Michel R.C.M. Berkelaar |
| title_full_unstemmed | Area-power-delay trade-off in logic synthesis door Michel R.C.M. Berkelaar |
| title_short | Area-power-delay trade-off in logic synthesis |
| title_sort | area power delay trade off in logic synthesis |
| topic | Computermethoden gtt Logica gtt Ontwerpen gtt VLSI gtt Logik Logischer Entwurf (DE-588)4168051-0 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Computermethoden Logica Ontwerpen VLSI Logik Logischer Entwurf Integrierte Schaltung Hochschulschrift |
| work_keys_str_mv | AT berkelaarmichelr areapowerdelaytradeoffinlogicsynthesis |