Digest of technical papers: November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional]
Gespeichert in:
| Körperschaft: | |
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| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. u.a.
IEEE Computer Soc. Press
1992
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XXV, 637 S. Ill., graph. Darst. |
| ISBN: | 0818630108 0818630116 0818630124 0897915402 0897915410 |
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| 245 | 1 | 0 | |a Digest of technical papers |b November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] |c IEEE, ACM International Conference on Computer-Aided Design |
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Datensatz im Suchindex
| _version_ | 1820868125925572608 |
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| adam_text |
TABLE
OF
CONTENTS
Foreword
.
v
Conference Committee
.
vi
Technical Program Committee
.
vii
Reviewers
.ix
Tutorial: Multi-Level Logic Synthesis
.xi
Tutorial: Interconnect and Packaging Analysis
.xii
Tutorial: Introduction to Embedded System Design
.xiii
Tutorial: Architectures for Software Systems
.xiv
Panel: University Faculty: Visionaries or Mercenaries?
. xv
Acknowledgements
.xvi
Session
1:
Plenary Session
Moderators: Michael
Lightner,
University of Colorado, Boulder, CO
Louise Trevillyan, IBM Corporation,
Yorktown
Heights, NY
Session 2A: DFT to Reduce Test Application Time
Moderators:
Wojciech Mały,
Carnegie Mellon University, Pittsburgh, PA
W. Kent
Fuchs,
University of Illinois,
Urbana,
IL
2A.1 Configuring Multiple Scan Chains for Minimum Test Time
.4
S. Narayanan, R. Gupta, and M.
Breuer
2A.2 Overall Consideration of Scan Design and Test Generation
.9
P.-C. Chen, B.-D. Liu, andJ.-F. Wang
2A.3 Configuration of a Boundary Scan Chain for Optimal Testing
of Clusters of
Non
Boundary Scan Devices
. 13
Y.-H. Choi and T. Jung
2A.4 An Algorithm to Reduce Test Application Time in Full Scan Designs
. 17
S. Y. Lee and K.K. Saluja
Session 2B: Technology Driven Layout
Moderators: M. Marek-Sadowska, University of California, Santa Barbara, CA
Majid Sarrafzadeh, Northwestern University, Evanston,
IL
2B.
1
New Channel Segmentation Model and Associated Routing
Algorithm for High Performance FPGAs
. 22
S.
Burman, C. Kamalanathan,
and
N.
Sherwani
2B.2 On Channel Segmentation Design for Row-Based FPGAs
. 26
K. Zhu and D.F. Wong
2B.3 VLSI Design Parsing
. 30
A. Tyagi
2B.4 Aesthetic Routing for Transistor Schematics
.,. 35
T.D. Lee and L.P. McNamee
Session 2C: Lookup Table Based FPGA Synthesis Techniques
Moderators: Richard Rudell, Synopsys, Inc., Mountain View, CA
Louise Treviilyan, IBM Corporation,
Yorktown
Heights, NY
2C.1-2 A Tutorial on Logic Synthesis for Lookup-Table Based FPGAs
.40
R.J. Francis
XVII
2C.3
An Optimal Technology Mapping Algorithm for Delay Optimization
in Lookup-Table Based FPGA Designs
.48
J. Cong and Y. Ding
2C.4 Rectification Method for Lookup-Table Type FPGA's
. 54
Y. Kukimoto and M. Fujita
Session
ЗА:
Advances in Asymptotic Waveform Evaluation
Moderators: Jacob K. White, Massachusetts Institute of Technology, Cambridge, MA
Andrzej Strojwas,
Carnegie Mellon University, Pittsburgh, PA
ЗАЛ
AWE Macromodels of VLSI Interconnect for Circuit Simulation
. 64
S.-Y. Kim,
N.
Gopal, and
LT.
Pillage
3A.2 Extension of the Asymptotic Waveform Evaluation Technique with
the Method of Characteristics
.71
J.E. Bracken, V. Raghavan, and R.A. Rohrer
3A.3 Numerical Integration Algorithms and Asymptotic Waveform
Evaluation (AWE)
.76
M.M. Alaybeyi, J.Y. Lee, andR.A. Rohrer
Session 3B: Topics in Simulation
Moderators:
Fabio Somenzi,
University of Colorado, Boulder, CO
Bill Read, Trilogy Development Group, Austin,
TX
3B.1 Timing Distribution in VHDL Behavorial Models
.82
A.S. Gadagkar and J.R. Armstrong
3B.2 McPOWER: A Monte Carlo Approach to Power Estimation
.90
R. Burch, F. Najm, P. Yang, andT. Trick
3B.3 Exhaustive Simulation Need Not Require an Exponential Number of Tests
.98
Đ.
Brand
Session 3C: Asynchronous Circuit Synthesis Using STG's
Moderators: Teresa H.-Y.
Meng,
Stanford University, Stanford, CA
David Dill, Stanford University, Stanford, CA
3C.1 A Unified Signal Transition Graph Model for Asynchronous
Control Circuit Synthesis
. 104
A. Yakovlev, L. Lavagno, and A. Sangiovanni-Vincentelli
3C.2 A Generalized State Assignment Theory for Transformations on
Signal Transition Graphs
. 112
P.
Vanbekbergen,
В.
Lin, G. Goossens, and H. De
Man
3C.3 On
the Verification of State-Coding in STGs
. 118
K.-J. Lin and C.-S. Lin
Session 4A; Clocking of Circuits with Level Sensitive Latches
Moderators: Sharad Malik, Princeton University, Princeton, NJ
Frans Theeuwen,
Eindhoven University of Tech., Eindhoven, The Netherlands
4АЛ
Verifying Clock Schedules
. 124
T.G. Szymanski and
N.
Shenoy
4A.2 Graph Algorithms for Clock Schedule Optimization
. 132
N.
Shenoy, R.K. Brayton, andA.L Sangiovanni-Vincentelli
4A.3 Identification of Critical Paths
т
Circuits with Level-Sensitive Latches
137
T.M. Burks, K.A. Sakallah, andT.N. Mudge
XVIII
4A.4
Using Constraint Geometry to Determine Maximum Rate
Pipeline Clocking
. 142
C.-H. Chang, E.S. Davidson, and K.A. Sakallah
Session 4B: High Density Module Assembly
Moderators: Tomoyuki Fujita, NEC Corporation, Kawasaki, Japan
M. Marek-Sadowska, University of California, Santa Barbara,
С А
4B.1 HIMALAYAS
-
A Hierarchical Compaction System with a
Minimized Constraint Set
. 150
J.-f. Lee and
D.T.Tang
4B.2 Cloning Techniques for Hierarchical Compaction
. 158
R. Varadarajan and C.S. Bamji
4B.3 An Optimal Chip Compaction Method Based on Shortest Path
Algorithm with Automatic Jog Insertion
. 162
T. Awashima, W. Yamamoto, M. Sato, and T. Ohtsuki
4B.4 MOSAIC: A Tile-Based Datapath Layout Generator
. 166
G. Suzuki, T. Yamamoto, K. Yuyama, and K. Hirasawa
Session 4C: Formal Hardware Verification
Moderators: David Dill, Stanford University, Stanford,
С А
Jean
Christophe
Madre,
Bull Research Center,
Les Clayes-sous-bois,
France
4C.1 Automatic Compositional Minimization in CTL Model Checking
. 172
M.
Chiodo,
T.R. Shiple, A.L. Sangiovanni-Vincentelli, and R.K. Brayton
4C.2 Verification of Systems Containing Counters
. 179
E.
Macii,
В.
Plessier, and
F. Somenzi
4C.3 Automatic Generation and Verification of Sufficient Correctness
Properties for Synchronous Processors
. 183
F. Van Aelten, S. Y. Liao, J. Allen, and S. Devadas
4C.4 Verification of Asynchronous Interface Circuits
with Bounded Wire Delays
. 188
5.
Devadas, K. Keutzer, S. Malik, and A. Wang
Session 5A: Techniques for Power and Tuning Estimation in CMOS Circuits
Moderators: Andrew T. Yang, University of Washington, Seattle, WA
Farid Najm, Texas Instruments, Inc., Dallas,
TX
5A.1 Delay and Bus Current Evaluation in CMOS Logic Circuits
. 198
A. Nabavi-Lishi and
N.
Rumin
5A.2 Power Estimation Tool for Sub-Micron CMOS VLSI Circuits
. 204
F. Rouatbi, B. Haroun, and A.J. Al-Khalili
5A.3 A Probabilistic Timing Approach to Hot-Carrier Effect Estimation
. 210
P.-C. Li, G.I. Stamoulis, and IN. Hajj
Session 5B: Sequential ATPG
Moderators: Tim Cheng, AT&T Bell Laboratories, Murray Hill, NJ
Sudhakar M. Reddy, University of Iowa, Iowa City, IA
5B.1
CRIS: A
Test Cultivation Program for Sequential VLSI Circuits
. 216
D.G. Saab, Y.G. Saab, andJ.A. Abraham
5B.2 Portable Parallel Test Generation for Sequential Circuits
. 220
B. Ramkumar and P. Banerjee
XIX
5B.3
Automatic
Test Generation for Linear Digital Systems with
Bi-Level Search Using Matrix Transform Methods
. 224
R.K. Roy, A. Chatterjee, J.H.
Patel,
J.
A. Abraham, andM.A.
d'Abreu
Session
SC:
High-Level Design
Moderators: Tsuguo Shimizu, Hitachi Ltd., Tokyo, Japan
Giovanni
De Micheli,
Stanford University, Stanford, CA
5C.1 An Effective Methodology for Functional Pipelining
. 230
T.-F. Lee, A. C.-H. Wu,
D.D.
Gajski, and Y.-L Lin
5C.2 A Scheduling Method by Stepwise Expansion in High-Level Synthesis
.234
Я.
Komi, S. Yamada, and K. Fukunaga
5C.3 Optimal Synthesis of Multichip Architectures
.238
C.H. Gebotys
Session 6A: Classical Simulation
Moderators: W. Van
Bokhoven,
Eindhoven University of Tech., Eindhoven, The Netherlands
Jacob K. White, Massachusetts Institute of Technology, Cambridge, MA
6A.
1
Analytic Macromodeling and Simulation of Tightly-Coupled
Mixed Analog-Digital Circuits
.244
Y.-H. Chang and A.T. Yang
6A.2 Automatic Differentiation in Circuit Simulation and Device Modeling
.248
P.
Feldmann,
R.
Melville, and S. Moinian
6A.3 A Methodology for Improved Circuit Simulation Efficiency Via
Topology-Based Variable Accuracy Device Modeling
.254
K. W. Michaels and A.J. Strojwas
6A.4 ETA: Electrical-Level Timing Analysis
.258
R.B. Brashear, D.R.
Holberg, M.R.
Mercer, andLT. Pillage
Session 6B: Testing and Diagnosis Methods
Moderators:
Javad
Khakbaz, Tandem Computers, Cupertino, CA
Melvin
Breuer,
University of Southern California, Los Angeles, CA
6B.
1
An Optimal Probe Testing Algorithm for the Connectivity
Verification of
MCM
Substrates
.264
S.-Z. Yao, M.-C.
Chou,
C.-K. Cheng, and T.C.
Ни
6B.2
Е
-PROOFS: A CMOS Bridging Fault Simulator
.268
G.S. Greenstein and J.H.
Patel
6B.3 On the Generation of Small Dictionaries for Fault Location
.272
/.
Pome
ranz andSM.
Reddy
6B.4 Efficient Partitioning and Analysis of Digital CMOS-Circuits
.280
U.
Hübner
and H.T.
Vierhaus
Session 6C: DSP Applications in High-Level Synthesis
Moderators:
Gert
Goossens,
ШЕС
Laboratory,
Leuven,
Belgium
Wayne Wolf, Princeton University, Princeton, NJ
6C.1 Efficiency Improvements for Force-Directed Scheduling
.286
W.FJ. Verhaegh, P.E.R,
Lippens, E.H.L Aarts, J.H.M. Korst,
A» van
der Werf,
and
J.L
van Meerbergen
бС.2
Area Optimization of Muiti-Functional Processing Units
.292
A. van
der Werf,
M
J.H. Peek, E.H.L
Aarts, J.L.
van
Meerbergen,
P.E.R.
Lippens,
and W.FJ. Verhaegh
xx
6C.3
HYPER-LP: A System for Power Minimization Using Architectural
Transformations
. 300
A. P.
Chandrakasan,
M.
Potkonjak, J. Rabaey, and R.W. Broder
sen
6C.4 Maximally Fast and Arbitrarily Fast Implementation
of Linear Computations
.304
M. Potkonjak and J. Rabaey
Session 7A: Analog CAD
Moderators: Rob
Rutenbar,
Carnegie Mellon University, Pittsburgh, PA
Ramesh Harjani, University of Minnesota, Minneapolis, MN
7
A.
1
Lazy-Expansion Symbolic Expression Approximation in
SYNAP
.310
S.J.
Seda,
M.G.R. Degrauwe, and W.
Fichtner
7A.2 Accurate Simplification of Large Symbolic Formulae
.318
F.V.
Fernández, A. Rodríguez-Vázquez, J.D. Martín, andJ.L Huertas
7A.3 Behavioral Simulation for Noise in Mixed-Mode Sampled-Data Systems
. 322
E.W.Y. Liu andA.L. Sangiovanni-Vincentelli
Session 7B: Multi-View Design Representations for Interactive Synthesis
Moderators: A. van
der Werf,
Philips Research Labs., Eindhoven, The Netherlands
R.
Gerber,
CNET/CNS/CCI, Meylan, France
7B.
1
An Efficient
Multi-
View Design Model for
Real-Time
Interactive Synthesis
.328
A.C.-H. Wu, T.S. Hadley, and
D.D.
Gajski
7B.2 Equivalent Design Representations and Transformations
for Interactive Scheduling
.332
R.P.
Ang andN.D.
Dutt
7B.3 FICOM: A Framework for Incremental Consistency Maintenance
in Multi-Representation, Structural VLSI Databases
. 336
R.C. Armstrong andJ. Allen
Session 7C: Timing in High Level Synthesis
Moderators: Raul Camposano, GMD/EIS,
Sankt
Augustin,
Germany
Daniel D. Gajski, University of California, Irvine, CA
7C.1 False Loops Through Resource Sharing
. 345
L. Stok
ICI
Timing Analysis in High-Level Synthesis
. 349
A. Kuehlmann and R.A.
Bergamaschi
7C.3 Accurate Layout Area and Delay Modeling for System Level Design
. 355
C. Ramachandran, F.J. Kurdahi,
D.D.
Gajski, A.C.-H. Wu, and V. Chaiyakul
Session 8A: Techniques for High Performance Simulation
Moderators: Peter Odryna, Precedence Inc.,
Scotts
Valley, CA
Gary York, Cadence Design Systems, Inc., Lowell, MA
8A.1 Ravel: Assigned-Delay Compiled-Code Logic Simulation.
. 364
EJ. Shriver andKA. Sakallah
8A.2 Parallel Logic and Fault Simulation Algorithms for Shared
Memory Vector Machines
. 369
A. Bataineh,
F. Özgüner,
and I. Szauter
8A.3
Reconfigurabłe
Machine and Its Application to Logic Diagnosis
. 373
N.
Suganuma, Y.
Murata,
S.
Nakata,
S. Nagata, M.
Tornita,
and K. Hirano
xxi
8A.4
A Logic Simulation Engine Based on a Modified Data Flow Architecture
. 377
A. Mahmood, W.I. Baker, J. Herath, and A. Jayasumana
Session 8B: Detailed Routing
Moderators:
Jochen A.G.
Jess, Eindhoven University of Tech., Eindhoven, The Netherlands
James Cohoon, University of Virginia, Charlottsville,
VA
8B.1 Maze Router Without a Grid Map
. 382
J.
Soukup
8B.2 Detailed Layer Assignment for
MCM
Routing
. 386
M. Sriram and S.M. Kang
8B.3 A Wire-Length Minimization Algorithm for Single-Layer Layouts
. 390
D.S.
Chen andM. Sarrafzadeh
8B.4 System-Level Routing of Mixed-Signal ASICs in WREN
. 394
S.
Mitra,
S.K. Nag, R.A.
Rutenbar,
and L. R. Carley
Session 8C: Topics in Logic Synthesis
Moderators:
Maciej
J. Cieselski, University of Massachusetts, Amherst, MA
Louise Trevfflyan, IBM Corporation,
Yorktown
Heights, NY
8C.1 On Average Power Dissipation and Random Pattern Testability
of CMOS Combinational Logic Networks
.402
A. Shen, A. Ghosh, S. Devadas, and K. Keutzer
8C.2 Efficient Boolean Function Matching
.408
J.R. Burch and
D.E.
Long
8C.3 ProperSYN: A Portable Parallel Algorithm for Logic Synthesis
. 412
K. De,
В.
Ramkumar, and P. Banerjee
8C.4 A New Algorithm for the
Binate
Covering Problem and Its Application
to the Minimization of Boolean Relations
. 417
S.-W. Jeong andF. Somenzi
Session 9A: Partitioning and Clustering
Moderators:
Antun
Domic, Digital Equipment Corporation, Hudson, MA
Kurt J. Antreich, Technical University of Munich, Munich, Germany
9A.1 A New Approach to Effective Circuit Clustering
.422
L
Hagen
and
A.B.
Kahng
9A.2 A Probabilistic Multicommodity-Flow Solution
to Circuit Clustering Problems
.428
C.-W. YehC.-K. Cheng, and T.-T.Y. Lin
9A.3 Optimal Replication for Min-Cut Partitioning
.432
J. Hwang and A. El Gamal
Session 9B: Interconnect Analysis
Moderators: Don
Scharfetter,
Intel Corporation, Santa Clara, CA
Lawrence T. Pillage, University of Texas, Austin,
TX
9B
. 1
Efficient Techniques for Inductance Extraction
of Complex
3-D
Geometries
.438
M. Kamon, MJ. Tsuk,
С
Smithhisler, and J. White
9B.2 An Analytical Method for Finding the Maximum Crosstalk
in Lossless-Coupled Transmission Lines
. 443
A. El-Zein andS. Chowdhury
XX»
9B.3
Time Domain Analysis of
Nonuniform
Frequency Dependent
High-Speed Interconnects
. 449
S.L. Manney, M.S. Nakhla, and Q.-j. Zhang
Session 9C: Engineering and Education: Trends and Needs
Moderators: Rob
Rutenbar,
Carnegie Mellon University, Pittsburgh, PA
Jacob K. White, Massachusetts Institute of Technology, Cambridge, MA
Speakers:
S.W.
Director, Carnegie Mellon University, Pittsburgh, PA
J. Allen, MIT, Cambridge, MA
J. Duley, Hewlett Packard, Palo Alto, CA
Session
10
A: High-Performance Routing
Moderators: Majid Sarrafzadeh, Northwestern University, Evanston,
IL
Jochen A.G.
Jess, Eindhoven University of Tech., Eindhoven, The Netherlands
10A.1 A Zero-Skew Clock Routing Scheme for VLSI Circuits
. 458
Y.-M. Li and
M.A. J abri
10A.2 Zero Skew Clock Routing in Multiple-Clock Synchronous Systems
. 464
W. Khan, M. Hossain, and
N.
Sherwani
10A.3 HERO: Hierarchical EMC-Constrained Routing
. 468
D. Theune, R.
Thiele,
T.
Lengauer, and
Α.
Feldmann
10A.4 Perfect-Balance Planar Clock Routing with Minimal Path-Length
. 473
Q. Zhu and W.W.-M. Dai
Session 10B: Hardware/Software Co-Design and System Design
Moderators: Hiroto Yasuura, Kyushu University, Fukuoka, Japan
Alfred E. Dunlop, AT&T Bell Labs., Murray Hill, NJ
10B.1 Design of System Interface Modules
.478
J.S. Sun andR.W. Brodersen
10B.2 A Partitioning Algorithm for System-Level Synthesis
. 482
G. Menez, M.
Auguin,
F.
Boèri,
and
С.
Carrière
10B.3
Synthesis of the Hardware/Software Interface
in Microcontroller-Based Systems
.488
P.
Chou,
R.
Ortega, and G. Borriello
10B.4 Assignment of Global Memory Elements for Multi-Process
VHDL Specifications
. 496
H.
Krämer
and J.
Müller
Session IOC: Retiming and Sensitization Conditions
Moderators: Patrick McGeer, University of California, Berkeley,
С А
Tohru Adachi, NTT LSI Labs., Kanagawa, Japan
IOC.
1
Performance Optimization of Sequential Circuits by Eliminating
Retiming Bottlenecks
.504
S. Dey, M.
Potkonjak, andS.G. Rothweiler
10C.2 Exploiting Multi-Cycle False Paths in the Performance Optimization
of Sequential Circuits
.510
P. Ashar,
S. Dey,
and S. Malik
10C.3 Valid Clocking in Wavepipelined Circuits
.518
W.K.C.
Lam, R.K.
В
ray ton, andA.L. Sangiovanni-Vincentelli
10C.4 Precise Timing Verification of Logic Circuits
under Combined Delay Model
.526
S. Kimura, S. Kashima, and H. Haneda
ХХШ
Session HA: Design Management
Styles
Moderators:
Sally Kleinfeldt,
Digital
Equipment
Corporation,
Littleton,
MA
Tamotsu Hiwatashi, Toshiba Corporation,
Kawasaki,
Japan
11
A.I DECOR
-
Tightly Integrated Design Control and Observation
.532
E.
Kupitz andJ. Tacken
11
A.2 Incorporating Design Flow Management in a Framework
Based CAD System
.538
P. Bingley, O. ten Bosch, and P. van
der Wolf
11
A.3 DAMOCLES: An Observer-Based Approach to Design Tracking
.546
V. Vasudevan, Y. Mathys, andJ.
Tolar
Session 11B: Delay Testing
Moderators: Nagisa Ishiura, Osaka University, Osaka, Japan
Patrick McGeer, University of California, Berkeley, CA
ПВ.1
Test Generation for Delay Faults in Non-Scan and Partial Scan
Sequential Circuits
.554
K.-T. Cheng
1
1B.2 An Efficient Non-Enumerative Method to Estimate Path
Delay Fault Coverage
.560
/.
Pomeraní
and S.M. Ready
1
1B.3 COMPACTEST-II: A Method to Generate Compact Two-Pattern Test
Sets for Combinational Logic Circuits
. 568
L.N. Reddy, I. Pomeranz, and S.M. Ready
Session 11C: Asynchronous Synthesis
Moderators:
Fabio Somenzi,
University of Colorado, Boulder, CO
Srinivas Devadas, Massachusetts Institute of Technology, Cambridge, CA
11C.1 Automatic Synthesis of
3D
Asynchronous State Machines
. 576
K.Y. Yun and
D.h.
Dill
11C.2 Automatic Gate-Level Synthesis of Speed-Independent Circuits
.581
P.A.
Beerei
and T.H.-Y.
Meng
1
1C.3 SHILPA: A High-Level Synthesis System for Self-Timed Circuits
.587
V. Akella and G. Gopalakrishnan
Session 12A: Placement and Floorplan Design
Moderators: Ralph Otten, Delft University of Technology, Delft, The Netherlands
Carl Sechen,
Yale University, New Haven, CT
1
2A.
1
Accurate Net Models for Placement Improvement
by Network Flow Methods
.594
K. Doll, F.M. Johannes, and G.
Sigi
12A.2 Three-Phase Chip Planning
-
An Improved Top-Down
Chip Planning Strategy
.598
B.
Schärmann,
J.
Altmeyer,
and
G.
Zimmermann
12A.3
Area Minimization for General Floorplans
.606
P. Pan and C.L Liu
Session 12B: High-Level View on Testing
Moderators: Bernard
Courtois,
МАйГПМЗ
Laboratory, Grenoble, France
William Rogers, University of Texas, Austin,
TX
XXIV
12В.
1
Behavioral Synthesis for Testability
. 612
C.-H. Chen andD.G. Saab
12B.2 Behavioral Synthesis for Easy Testability in Data Path Scheduling
. 616
T.-C. Lee, W.H. Wolf, andN.K. Jha
1
2B.3 A Comparative Study of Design for Testability Methods Using
High-Level and Gate-Level Descriptions
. 620
V. Chickermane, J. Lee, and J.H.
Patel
Session 12C: Hazards in Combinational Synthesis
Moderators: Masahiro Fujita, Fujitsu Labs., Ltd., Kawasaki, Japan
Richard Rudell, Synopsys,
Im.,
Mountain View, CA
1
2C.
1
Exact Two-Level Minimization of Hazard-Free Logic with
Multiple-Input Changes
. 626
S.M. Nowick and D.L. Dill
12C.2 Hazard-Non-Increasing Gate-Level Optimization Algorithms
. 631
D.S.
Kung
Author Index
. 635
xxv |
| any_adam_object | 1 |
| author_corporate | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) Santa Clara, Calif |
| author_corporate_role | aut |
| author_facet | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) Santa Clara, Calif |
| author_sort | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) Santa Clara, Calif |
| building | Verbundindex |
| bvnumber | BV008231273 |
| classification_rvk | ZG 9146 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)311634982 (DE-599)BVBBV008231273 |
| dewey-full | 621.3815/0285 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/0285 |
| dewey-search | 621.3815/0285 |
| dewey-sort | 3621.3815 3285 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Technik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 1992 Santa Clara Calif. |
| id | DE-604.BV008231273 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:19:24Z |
| institution | BVB |
| institution_GND | (DE-588)5089386-5 |
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| language | English |
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| physical | XXV, 637 S. Ill., graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | IEEE Computer Soc. Press |
| record_format | marc |
| spelling | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) 10 1992 Santa Clara, Calif. Verfasser (DE-588)5089386-5 aut Digest of technical papers November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] IEEE, ACM International Conference on Computer-Aided Design Los Alamitos, Calif. u.a. IEEE Computer Soc. Press 1992 XXV, 637 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Konsumelektronik (DE-588)4165117-0 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1992 Santa Clara Calif. gnd-content VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s CAD (DE-588)4069794-0 s DE-604 Layout Mikroelektronik (DE-588)4264372-7 s 1\p DE-604 Integrierte Schaltung (DE-588)4027242-4 s 2\p DE-604 Logische Schaltung (DE-588)4131023-8 s 3\p DE-604 Konsumelektronik (DE-588)4165117-0 s 4\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005432851&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Digest of technical papers November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] Logische Schaltung (DE-588)4131023-8 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Konsumelektronik (DE-588)4165117-0 gnd Entwurf (DE-588)4121208-3 gnd CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4131023-8 (DE-588)4027242-4 (DE-588)4264372-7 (DE-588)4165117-0 (DE-588)4121208-3 (DE-588)4069794-0 (DE-588)4117388-0 (DE-588)1071861417 |
| title | Digest of technical papers November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] |
| title_auth | Digest of technical papers November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] |
| title_exact_search | Digest of technical papers November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] |
| title_full | Digest of technical papers November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] IEEE, ACM International Conference on Computer-Aided Design |
| title_fullStr | Digest of technical papers November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] IEEE, ACM International Conference on Computer-Aided Design |
| title_full_unstemmed | Digest of technical papers November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] IEEE, ACM International Conference on Computer-Aided Design |
| title_short | Digest of technical papers |
| title_sort | digest of technical papers november 8 12 1992 santa clara california iccad 92 a conference for the ee cad professional |
| title_sub | November 8 - 12, 1992, Santa Clara, California ; [ICCAD-92, a Conference for the EE CAD Professional] |
| topic | Logische Schaltung (DE-588)4131023-8 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Konsumelektronik (DE-588)4165117-0 gnd Entwurf (DE-588)4121208-3 gnd CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Logische Schaltung Integrierte Schaltung Layout Mikroelektronik Konsumelektronik Entwurf CAD VLSI Konferenzschrift 1992 Santa Clara Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005432851&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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