Synthesis for control dominated circuits: selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Amsterdam u.a.
North-Holland
1993
|
| Schriftenreihe: | International Federation for Information Processing: [IFIP transactions / A]
22 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | IX, 453 S. graph. Darst. |
| ISBN: | 0444814795 |
Internformat
MARC
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| 245 | 1 | 0 | |a Synthesis for control dominated circuits |b selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 |c ed. by Gabrièle Saucier ... |
| 264 | 1 | |a Amsterdam u.a. |b North-Holland |c 1993 | |
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| 490 | 1 | |a International Federation for Information Processing: [IFIP transactions / A] |v 22 | |
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| 650 | 7 | |a Circuits intégrés à la demande - Congrès |2 ram | |
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| 650 | 7 | |a Micro-elektronica |2 gtt | |
| 650 | 7 | |a agencement circuit |2 inriac | |
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| 650 | 7 | |a architecture multicouche en tranche |2 inriac | |
| 650 | 7 | |a controleur circuit integre |2 inriac | |
| 650 | 7 | |a controleur complexe |2 inriac | |
| 650 | 7 | |a controleur hierarchique |2 inriac | |
| 650 | 7 | |a controleur parallele |2 inriac | |
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Datensatz im Suchindex
| _version_ | 1820868123621851136 |
|---|---|
| adam_text |
rtf, s
A-22
/SYNTHESIS FOR
CONTROL
DOMINATED
CIRCUITS
Selected papers from the IFIP WG10 2/WG10 5 Workshops
Grenoble, France, April and September, 1992
Edited by
GABRIELE SAUCIER
INPG/CSI Laboratory
Grenoble, France
JACQUES TRILHE
JESSI Office Organization
Munich, Germany
NachjiehtentwhiMschc Bibliothek
t; id
lnv -Nr :
A3H 130
1993
NORTH-HOLLAND
AMSTERDAM • LONDON • NEW YORK • TOKYO
Vll
Contents
Chapter L FSM Synthesis
RTL Controller Synthesis
C Huang, J Lis, M Quayle, S Shroff 3
Timing-Driven State Assignment for Controller-Datapath
Systems
S C -Y Huang, W Wolf 19
Tokenized State Machine Model for Synthesis of Sequential
Circuits into EPLDs and FPGAs
A Coppola, M A Perkowski, R Anderson,
J S Freedman, E Pierzchala 33
Synthesis of large controllers using ROM or PLA generators
L Gerbaux, R Leveugle, G Saucier 47
Flag/Condition Handling and Branch Assignment for
Large Microcoded Controllers
A Kifli, R De Wulf, J Zegers, G Goossens,
P Six, H De Man 61
The Synthesis of a Parallel Controller from a Petri Net Model
J Pardey 73
Specification and Synthesis of Communicating Finite State
Machines
H Belhadj, L Gerbaux, M -C Bertrand, G Saucier 91
Controller Implementation by Communicating Asynchronous
Sequential Circuits Generated from a Petri Net Specification of
Required Behavior
J Beister, R Wollowski 103
Vlll
Chapter II: Data-path
Pathway: A datapath layout assembler
A Baron Cohen, M Shechory 119
FITPATH: A Process-Independent Datapath Compiler
Providing High Density Layout
L Ben Ammar, A Greiner 133
Generation of optimized datapaths: bit-slice versus standard cells
R Leveugle, C Safinia 153
Regular Module Generation or Standard Cells: Two Alternative
Implementations of a Library of Functional Building Blocks
E Katsadas, Z Sahraoui, M Wouters,
V Derudder, I Bolsens, P Six, H De Man 167
Design of data-path module generators from algorithmic
representations
V Moshnyaga, K Tamaru, H Yasuura 183
Data-Path Synthesis as Grammar Inference
F Mavaddat 193
Chapter Eli: RTL Synthesis
Microarchitecture/Microcode Synthesis from VHDL
E T Kapuya, M D Edwards 209
AMICAL: Architectural Synthesis based on VHDL
I Park, K O'Brien, A A Jerraya 219
RTLOptimizA: From Control Data Flow Graph to Logic Circuit
Y Wu, I Dorrington 235
Implementations of IF-statements in the TODOS microarchitecture
synthesis system
P Marwedel 249
Data Part Optimizations in the CALLAS Synthesis Environment
J Biesenack, N Wehn, A Stoll, M Payer 263
ASYL: A Control Driven RTL Synthesis System using Library
Blocks
A Mignotte, M -C Bertrand, M Crastes de Paulet,
J Rampon, G Saucier 275
IX
Clocking scheme selection for circuits made up of a controller
and a datapath
C Safinia, R Leveugle 293
Chapter IV: Module generation
Optimization strategies in symbolic compaction
F Curatelli, D D Caviglia, M Chirico, G M Bisio 311
A general and efficient mask pattern generator for non-series-
parallel CMOS transistor network
H Zhang, K Asada 323
Logic Synthesis for Automatic Layout
P Abouzeid, R Leveugle, G Saucier 335
MADMACS: an environment for the layout of regular arrays
E Gautrin, L Perraudeau 345
Module Generation in an Architectural Synthesis Environment
JFM Theeuwen, HMAM Arts, JTJ van Eijndhoven,
HJH Sleuters, JHP Wijdeven 359
BADGE - A synthesis tool for customized arithmetic building blocks
A Münzner 373
Automatic Layout Synthesis of Pipelined Multipliers for
Systolic Arrays
A G Jost, L F Wang, S Periyalwar, W Robertson 385
Floorplan Optimized Topological Partitioning of Programmed
Logic Arrays
AJWM ten Berg 399
Timing Model Accuracy Issues and Automated Library
Characterization
A Martinez 413
Design Library Portability: A Case Study
B Conq, R Etienne, T Perez-Segovia 427
Invited paper
Benchmarking and the Art of Synthesis Tool Comparison
D D Gajski, N D Dutt |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV008019562 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.6 |
| callnumber-search | TK7874.6 |
| callnumber-sort | TK 47874.6 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | SS 1992 |
| ctrlnum | (OCoLC)27727223 (DE-599)BVBBV008019562 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| genre_facet | Konferenzschrift 1992 Grenoble |
| id | DE-604.BV008019562 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:19:22Z |
| institution | BVB |
| isbn | 0444814795 |
| language | English |
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| physical | IX, 453 S. graph. Darst. |
| publishDate | 1993 |
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| publisher | North-Holland |
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| series2 | International Federation for Information Processing: [IFIP transactions / A] |
| spelling | Synthesis for control dominated circuits selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 ed. by Gabrièle Saucier ... Amsterdam u.a. North-Holland 1993 IX, 453 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier International Federation for Information Processing: [IFIP transactions / A] 22 Circuits intégrés - Simulation par ordinateur - Congrès ram Circuits intégrés à la demande - Congrès ram Controlling gtt Micro-elektronica gtt agencement circuit inriac architecture cellulaire inriac architecture multicouche en tranche inriac controleur circuit integre inriac controleur complexe inriac controleur hierarchique inriac controleur parallele inriac Application specific integrated circuits Design Congresses Electronic controllers Design Congresses Logic design Congresses Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1992 Grenoble gnd-content Kundenspezifische Schaltung (DE-588)4122250-7 s DE-604 Saucier, Gabrièle Sonstige oth A] International Federation for Information Processing: [IFIP transactions 22 (DE-604)BV006188900 22 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005276420&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Synthesis for control dominated circuits selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 Circuits intégrés - Simulation par ordinateur - Congrès ram Circuits intégrés à la demande - Congrès ram Controlling gtt Micro-elektronica gtt agencement circuit inriac architecture cellulaire inriac architecture multicouche en tranche inriac controleur circuit integre inriac controleur complexe inriac controleur hierarchique inriac controleur parallele inriac Application specific integrated circuits Design Congresses Electronic controllers Design Congresses Logic design Congresses Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)1071861417 |
| title | Synthesis for control dominated circuits selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 |
| title_auth | Synthesis for control dominated circuits selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 |
| title_exact_search | Synthesis for control dominated circuits selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 |
| title_full | Synthesis for control dominated circuits selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 ed. by Gabrièle Saucier ... |
| title_fullStr | Synthesis for control dominated circuits selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 ed. by Gabrièle Saucier ... |
| title_full_unstemmed | Synthesis for control dominated circuits selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 ed. by Gabrièle Saucier ... |
| title_short | Synthesis for control dominated circuits |
| title_sort | synthesis for control dominated circuits selected papers from the ifip wg10 2 wg10 5 workshops grenoble france april and september 1992 |
| title_sub | selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September, 1992 |
| topic | Circuits intégrés - Simulation par ordinateur - Congrès ram Circuits intégrés à la demande - Congrès ram Controlling gtt Micro-elektronica gtt agencement circuit inriac architecture cellulaire inriac architecture multicouche en tranche inriac controleur circuit integre inriac controleur complexe inriac controleur hierarchique inriac controleur parallele inriac Application specific integrated circuits Design Congresses Electronic controllers Design Congresses Logic design Congresses Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| topic_facet | Circuits intégrés - Simulation par ordinateur - Congrès Circuits intégrés à la demande - Congrès Controlling Micro-elektronica agencement circuit architecture cellulaire architecture multicouche en tranche controleur circuit integre controleur complexe controleur hierarchique controleur parallele Application specific integrated circuits Design Congresses Electronic controllers Design Congresses Logic design Congresses Kundenspezifische Schaltung Konferenzschrift 1992 Grenoble |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005276420&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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