Systematic design of regular VLSI processor arrays:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | Dutch English |
| Published: |
1990
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| Subjects: | |
| Item Description: | Delft, Techn. Univ., Diss., 1990 |
| Physical Description: | V, 137 S. graph. Darst. |
Staff View
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Record in the Search Index
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| author | Bu, Jichun |
| author_facet | Bu, Jichun |
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| author_sort | Bu, Jichun |
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| building | Verbundindex |
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| illustrated | Illustrated |
| indexdate | 2024-07-09T16:57:58Z |
| institution | BVB |
| language | Dutch English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-004627094 |
| oclc_num | 256022348 |
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| owner_facet | DE-91 DE-BY-TUM |
| physical | V, 137 S. graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
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| spelling | Bu, Jichun Verfasser aut Systematic design of regular VLSI processor arrays door Jichun Bu 1990 V, 137 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Delft, Techn. Univ., Diss., 1990 Mehrprozessorsystem (DE-588)4038397-0 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Entwurf (DE-588)4121208-3 s Mehrprozessorsystem (DE-588)4038397-0 s VLSI (DE-588)4117388-0 s DE-604 |
| spellingShingle | Bu, Jichun Systematic design of regular VLSI processor arrays Mehrprozessorsystem (DE-588)4038397-0 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4038397-0 (DE-588)4121208-3 (DE-588)4117388-0 (DE-588)4113937-9 |
| title | Systematic design of regular VLSI processor arrays |
| title_auth | Systematic design of regular VLSI processor arrays |
| title_exact_search | Systematic design of regular VLSI processor arrays |
| title_full | Systematic design of regular VLSI processor arrays door Jichun Bu |
| title_fullStr | Systematic design of regular VLSI processor arrays door Jichun Bu |
| title_full_unstemmed | Systematic design of regular VLSI processor arrays door Jichun Bu |
| title_short | Systematic design of regular VLSI processor arrays |
| title_sort | systematic design of regular vlsi processor arrays |
| topic | Mehrprozessorsystem (DE-588)4038397-0 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Mehrprozessorsystem Entwurf VLSI Hochschulschrift |
| work_keys_str_mv | AT bujichun systematicdesignofregularvlsiprocessorarrays |