Systematic design of regular VLSI processor arrays:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | Dutch English |
| Veröffentlicht: |
1990
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| Schlagworte: | |
| Beschreibung: | Delft, Techn. Univ., Diss., 1990 |
| Beschreibung: | V, 137 S. graph. Darst. |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV007221792 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 930505s1990 d||| m||| 00||| dutod | ||
| 035 | |a (OCoLC)256022348 | ||
| 035 | |a (DE-599)BVBBV007221792 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a dut |a eng | |
| 049 | |a DE-91 | ||
| 084 | |a ELT 272d |2 stub | ||
| 084 | |a DAT 212d |2 stub | ||
| 100 | 1 | |a Bu, Jichun |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Systematic design of regular VLSI processor arrays |c door Jichun Bu |
| 264 | 1 | |c 1990 | |
| 300 | |a V, 137 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Delft, Techn. Univ., Diss., 1990 | ||
| 650 | 0 | 7 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 0 | 1 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |D s |
| 689 | 0 | 2 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-004627094 | ||
Datensatz im Suchindex
| _version_ | 1804121437000171520 |
|---|---|
| any_adam_object | |
| author | Bu, Jichun |
| author_facet | Bu, Jichun |
| author_role | aut |
| author_sort | Bu, Jichun |
| author_variant | j b jb |
| building | Verbundindex |
| bvnumber | BV007221792 |
| classification_tum | ELT 272d DAT 212d |
| ctrlnum | (OCoLC)256022348 (DE-599)BVBBV007221792 |
| discipline | Informatik Elektrotechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01181nam a2200373 c 4500</leader><controlfield tag="001">BV007221792</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">930505s1990 d||| m||| 00||| dutod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)256022348</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV007221792</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">dut</subfield><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 272d</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 212d</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bu, Jichun</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Systematic design of regular VLSI processor arrays</subfield><subfield code="c">door Jichun Bu</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1990</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">V, 137 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Delft, Techn. Univ., Diss., 1990</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-004627094</subfield></datafield></record></collection> |
| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV007221792 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:57:58Z |
| institution | BVB |
| language | Dutch English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-004627094 |
| oclc_num | 256022348 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | V, 137 S. graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| record_format | marc |
| spelling | Bu, Jichun Verfasser aut Systematic design of regular VLSI processor arrays door Jichun Bu 1990 V, 137 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Delft, Techn. Univ., Diss., 1990 Mehrprozessorsystem (DE-588)4038397-0 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Entwurf (DE-588)4121208-3 s Mehrprozessorsystem (DE-588)4038397-0 s VLSI (DE-588)4117388-0 s DE-604 |
| spellingShingle | Bu, Jichun Systematic design of regular VLSI processor arrays Mehrprozessorsystem (DE-588)4038397-0 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4038397-0 (DE-588)4121208-3 (DE-588)4117388-0 (DE-588)4113937-9 |
| title | Systematic design of regular VLSI processor arrays |
| title_auth | Systematic design of regular VLSI processor arrays |
| title_exact_search | Systematic design of regular VLSI processor arrays |
| title_full | Systematic design of regular VLSI processor arrays door Jichun Bu |
| title_fullStr | Systematic design of regular VLSI processor arrays door Jichun Bu |
| title_full_unstemmed | Systematic design of regular VLSI processor arrays door Jichun Bu |
| title_short | Systematic design of regular VLSI processor arrays |
| title_sort | systematic design of regular vlsi processor arrays |
| topic | Mehrprozessorsystem (DE-588)4038397-0 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Mehrprozessorsystem Entwurf VLSI Hochschulschrift |
| work_keys_str_mv | AT bujichun systematicdesignofregularvlsiprocessorarrays |