Proceedings of the 1991 International Conference on Microelectronic Test Structures: March 18 - 20, 1991, Kyoto, Japan
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| Format: | Tagungsbericht Buch |
| Sprache: | Undetermined |
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New York, NY
Inst. of Electrical and Electronics Engineers
1991
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XII, 264 S. Ill., graph. Darst. |
| ISBN: | 0879425881 087942589X 0879425903 |
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| adam_text | 1991
PROCEEDINGS ON
MICROELECTRONIC TEST STRUCTURES
March
1991,
Volume
4
91CH2907-4
Library of Congress No.
90-82543
1991
IEEE INTERNATIONAL CONFERENCE ON
MICROELECTRONIC TEST STRUCTURES (ICMTS)
Kyoto Grand Hotel, Kyoto, Japan
March
18-20, 1991
CONTENTS
CHAIRPERSON S LETTER
.........................................
vii
CONFERENCE COMMITTEE
.........................................viii
STEERING COMMITTEE
......................................... ix
TECHNICAL COMMITTEE
.........................................ix
PROGRAM SESSIONS AND CHAIRPERSONS
.........................................
χ
1992
CONFERENCE INFORMATION
.........................................xi
RECAP OF
1990.........................................xii
AUTHOR S INDEX
.........................................263
Session I
Test Structures for Material and Process Characterization I
Material and Process Learning by Non-Contact Characterization of Minority Carrier
Lifetime and Surface Recombination Condition (invited paper)
............................. 1
A. Usami,
Nagoya Institute of Technology, Nagoya, Japan
Extraction of the
Interfacial
Generation Velocity in MOSFET s
.............................11
/.
Dugas,
R. Jérisian, J.
Ouaiid,
D.
Labrunye* and J.
M.
Mirabel*,
ENSPM, Domaine
Univerritaire de
Smnt-Jérôme,
Marseille, France
*SGS Thomson Microelectronks, Romset, France
Edge Effect Prediction
in Real
MOS
Insulator Using Test Chips
.............................17
/.
Yugami and A. Hiraiwa,
Hitachi Ltd., Tokyo, Japan
Session
Π
Test Structures for Material and Process Characterization
Π
A Meîhodology
for Evaluating the Area of Contacts to Improve the Accuracy of
Contact Resistance Measurements
............................23
A. J. Walton, M.
Fallon,
J.
T. M. Stevenson, A. Ross
and JR.
J.
Holwill
University of Edinburgh, Edinburgh, UK
The Vertical Test Structure for Measuring Contact Resistance between Two Kinds
of Metal
............................29
S.
Ido,
M. Imai, T. Kumise, M. Satoh, H. Horie and S.
Ando
Fujitsu Laboratories, Ltd., Atsugi,
Japan
Test Chip for the
Evaluation
of
Surface Diffusion
Phenomena in Sputtered Aluminum
Planarization Processes
............................35
M. A. Jones, J. A.
Roberts,
С.
H.
Ellenwood*,
M.
W.
Cresswell* and R. A. Allen*
Eaton Corporation, Beverly, MA, USA,
*National
Institute
of Standards and Technology, Gaithersburg,
MD, USA
Session
ΙΠ
Test Structures for Material and Process Characterization
Ш
A New Structure for Measuring the Thermal Conductivity of Integrated Circuit
Dielectrics
............................41
J. H. Orchard-Webb
Mitel Semiconductor, Kanata, Ontario, Canada
.
An
MOS
Test Device with the Gate Electrode Emphasized for Dielectric Breakdown
..........47
Y. Tatewaki, K. Matsuda, K. Tanaka, K. Nishizawa and
K. Satöyatna
Sharp Corporation, Tenri, Japan
Analysis of Process Induced Charges Created in MOSFETs and Related Collection Test
Structures
............................51
P. Dars, R. Basset and G.
МегсЫ
CNET-CNS, Meylan, France
Gate Oxide Thickness Measurement Using Fowler-Nordheim Tunneling
.................57
R. A. Ashton
ΑΤάΤ
Bell Laboratories, Allentown, PA, USA
Session
ГУ
Test Structures for Reliability Analysis I
Test Structures to Investigate Thin Insulator Dielectric Wearout and Breakdown
(invited paper)
...........................61
D. J. Dumin,
N.
B. Heilemam and
N.
Húsain
Center for Semiconductor Device Reliability Research, Clemson University,
Clemson, SC, USA
Evaluation of Gate Oxide Reliability Using Luminescence Method
.,.........................69
Y. Uraoka, H. Yoshikawa,
N.
Tsutsu and S. Akiyama
Matsushita Electric Industrial Co., Ltd., Moriguchi, Japan
il
Dependence of Dielectric Time to Breakdown Distributions on Test Structure Area
........75
R.-P. Vollertsen and W. G. Kleppmann
Siemens
AG,
München,
Germany
Accelerated Current Test for Fast Tunnel Oxide Evaluation
.............................81
P.
Cappelletti,
P. Ghezzi, F.
Pio
and
С
Riva
SGS-Thomson, Central R&D,
Agrate
Brianza (MI), Italy
Novel Measurement Technique for Trapped Charge Centroid in Gate Insulator
........87
J. Kwnagai, S. Sawada and K. Toita
Toshiba Corporation, Kawasaki, Japan
Session V
Circuit Oriented Test Structures
Simple Evaluation of Very Low Currents in Process Characterization
............................93
P.
Girard, P.
Nouet and
F. M.
Roche
LAMM,
Université de Montpellier
II,
Montpellier, France
Trench DRAM Structures
for the Analysis of Two- and Three- Dimensional Leakage
Phenomena
............................97
S. H. Voldman
IBM General Technology Division, Essex Junction,
VT, USA
A Technique for Measuring Threshold Mismatch in DRAM Sense Amplifier Devices
......103
E. J. Sprogis
IBM General Technology Division, Essex Junction,
VT, USA
The Inverter Matrix: A Vehicle for Assessing Process Quality through Inverter
Parameter Analysis of Variance
..........................107
D. J.
Hannaman,
M. G.
Buehler*, J. Chang* and
H. R.
Sayah*
Silicon Systems Incorporated, Tustin, CA, USA
*Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA
Test SRAMs for Characterizing Alpha Particle Tracks in CMOS/Bulk Memories
......113
M. G. Buehler, B. R. Blaes and G. A. Soli
Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA
Session VI
Test Structures for Dimensional Control
Improvement of the Triangular
MOS
Transistor
for Misalignment Measurement
......119
M.
Lozano,
С.
Cani,
С.
Percllâ,
J.
Anguila
and
E.
Lora
-Татауо
CNM,
Universidad Autónoma
de Barcelona, Barcelona,
Spain
X-ray Exposure Mask Accuracy Evaluation Using Electrical Test Structures
................123
Y. KuroU, S. Hasegawa, T. Honda and Y.
lida
NEC Corporation, Sagaminara, Japan
A Modified Sliding Wire Potentiometer Test Structure for Mapping Nanometer-Level
Distances
..........................129
M. W. Cresswett, M.
Găitan,
R.
A, Allen and L. W. Unholm
National Institute of
Standards
and Technology, Gaithersburg,
MD, USA
m
Fułły-Automated
Line-width Measurement System and Its Applications
...........................135
M. Yoshizawa and K.
Wada
NTT LSI Laboratories, Atsugi, Japan
Session
VII
Posters
Yield Management Test Sites
...........................141
A. V. S. Satya
IBM Corporation, East Fishkill Facility, Hopewell Junction, NY, USA
Knowledge Verification of Machine-Learning Procedures Based on Test
Structure Measurements
...........................145
D. Khera, L. W. Linholm, R. A. Allen, M. W. Cresswell, V.
С
Tyree*,
W.
Hansford*
and
C. Pina*
National Institute of Standards and Technology, Gaithersburg,
MD, USA
*University of Southern California, Marina del
Rey,
CA,
USA
Standardization of Test Structure Design
...........................151
C. Weber
Hewlett-Packard Corporation, Palo Alto, CA, USA
Examination of LOCOS Process Parameters and the Measurement of Effective Width
......157
M.
Fallon,
J. M.
Robertson, A. J. Walton
and R. J. Holwill
EMF,
University of Edinburgh, Edinburgh, UK
Session
VIII
Test Structures for Dopant Distribution Analysis
A New Set of Electrical Test Structures for Simultaneous Single-Wafer Monitoring
of Ion Implant Shadowing, Channeling, and Dose Uniformity
...........................163
A. M. McCarthy and W. Lukmzek
Stanford University, Stanford, CA, USA
Measurement of Lateral Diffusion Profiles for Submicrometer MOSFET s
...........................169
K. Kubota, Y. Kawashima*, S. Yoshida** and M. Ishida
Hitachi Ltd., Tokyo, Japan
*Hitachi Microcomputer System Ltd., Tokyo, Japan
**Hitachi VLSI Engineering Corporation, Tokyo, Japan
Measurement of Lateral Diffusion on Technologies with Polysfficon Doping Source
with Misalignment Correction
...........................175
/.
Anguita, C.
Perelló,
M.
Lozano,
С.
Cane and E.
Lora
-Татауо
CNM,
Universidad
Autònoma de
Barcelona, Barcelona,
Spain
Test
Structure
for Determining
Boroa
Diffusion Coefficient in Tungsten Suicide
.................179
Y. Kataoka, K. Suzuki, H. Horie, Y. Yamashita,
N.
Nakayama and T. Kitakohji,
Fujitsu Laboratories, Ltd., Atsugi, Japan
Lateral Spread of High Energy Implanted Ions Studied by Electronic Test
Structures
...........................183
T. Ueda, H.
АоЫ,
Y.
Kinoshìta,
S.
Wada,
H. Miyatake,
J.
Kudo
and T. Ashida
Sharp Corporation,
Tenu,
Japan
Session
IX
Modeling and Parameter Extraction I
Progress on Model Building and Statistical Analysis Methodology of
1С
Characteristics with Process (invited paper)
...........................189
H. Yie and Y. Jiannan
Southeast University, Nanjing, People s Republic of China
Direct Extraction of Accurate DC Bipolar SPICE Parameters for the Forward
Active Region Without Using Optimization
...........................197
J. Kendall
Northern Telecom Electronics, Nepean, Ontario, Canada
A New Bipolar Extraction Tool for Wide Range of Device Behaviours
...........................203
E. Mazaleyrat, D.
Celi,
A. Juge
and B, Cialdella
SGS Thomson Microelectronics, Grenoble, France
Session X
Modeling and Parameter Extraction
Π
MOSFET Statistical Parameter Extraction Using Multivariate Statistics
...........................209
/.
A. Power, A. Mathewson and W. A. Lane
National Microelectronics Research Centre, Cork City, Ireland
A New Effective Channel Length Determination Method for LDD MOSFETs
.................215
K. Takeuchi,
N.
Kasai
and K. Terada
NEC Corporation, Sagamihara, Japan
Semiconductor Device Parameter Extraction Based on
Reconfigurable
Ring Oscillator
Frequency Measurements
...........................221
F.
Kovács
and G.
Hosszú
Technical University of Budapest, Budapest, Hungary
Session XI
Test Structures for Reliability Analysis
Π
Novel Test Structures for the Characterization of Latch-up Tolerance in a Bipolar
and MOSFET Merged Device
...........................225
H.
Marnose,
T.
Maeda,
K. Inom,
Y. Urakawa and K. Maeguchi
Toshiba Corporation, Kawasaki,
Japan
Photoemission
Identification
of Emitter Resistance for CMOS Latch-Up Hysteresis
......231
M.-J. Chen, J.-K. Jeng*. P.-N. Tseng** N.-S. Tsai** and C.-Y. Wu
National Chiao-Tung University,
Нмп
-Chu,
Taiwan, Republic of China,
*Electronics Research and Service Organization, Hsin-Chu, Taiwan, Republic of China,
**Tatwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, Taiwan, Republic of
China
A Hot Carrier Parallel Testing Technique to Bring the Reliable Extrapolation
................237
N.
Koike, M.
Ito
and H. Kuriyama
Matsushita Electronics Corporation, Kyoto, Japan
Gate Chain Structures with On-Chip Clock Generators for Realistic High-Speed
Dynamic Stress
...........................241
N.
Shiono and
Г»
Mizusawa
ΝΤΓ
LSI Laboratories, Atsugi, Japan
Session
XII
Test Structures for Reliability Analysis III
An Ovenless Electromigration Test System Environment Using Test Chips with
On-chip Heating and Computer Controlled Testing
...........................245
V. C. Tyree
University of Southern California, Marina del
Rey,
СА,
USA
Study of Electromigration at Interconnect
Vias
...........................251
T.
Wada,
I. Matsuo and T. Umemoto
Matsushita Electronics Corporation, Kyoto, Japan
A Fast Testing of ElectromigratioD Immunity Using Noise Measurement
Technique
...........................257
/.
Komori,
Y.
Tokáta,
J.
Mitsuhashì
and
N.
Tsubouchi
Mitsubishi Electric Corporation,
Itami,
Japan
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| spelling | ICMTS 4 1991 Kyōto Verfasser (DE-588)5059509-X aut Proceedings of the 1991 International Conference on Microelectronic Test Structures March 18 - 20, 1991, Kyoto, Japan ICMTS 1991 New York, NY Inst. of Electrical and Electronics Engineers 1991 XII, 264 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Mikroelektronik (DE-588)4039207-7 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf Kyōto (DE-588)4073426-2 gnd rswk-swf (DE-588)1071861417 Konferenzschrift gnd-content Mikroelektronik (DE-588)4039207-7 s Prüftechnik (DE-588)4047610-8 s Kyōto (DE-588)4073426-2 g DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=003793911&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the 1991 International Conference on Microelectronic Test Structures March 18 - 20, 1991, Kyoto, Japan Mikroelektronik (DE-588)4039207-7 gnd Prüftechnik (DE-588)4047610-8 gnd |
| subject_GND | (DE-588)4039207-7 (DE-588)4047610-8 (DE-588)4073426-2 (DE-588)1071861417 |
| title | Proceedings of the 1991 International Conference on Microelectronic Test Structures March 18 - 20, 1991, Kyoto, Japan |
| title_auth | Proceedings of the 1991 International Conference on Microelectronic Test Structures March 18 - 20, 1991, Kyoto, Japan |
| title_exact_search | Proceedings of the 1991 International Conference on Microelectronic Test Structures March 18 - 20, 1991, Kyoto, Japan |
| title_full | Proceedings of the 1991 International Conference on Microelectronic Test Structures March 18 - 20, 1991, Kyoto, Japan ICMTS 1991 |
| title_fullStr | Proceedings of the 1991 International Conference on Microelectronic Test Structures March 18 - 20, 1991, Kyoto, Japan ICMTS 1991 |
| title_full_unstemmed | Proceedings of the 1991 International Conference on Microelectronic Test Structures March 18 - 20, 1991, Kyoto, Japan ICMTS 1991 |
| title_short | Proceedings of the 1991 International Conference on Microelectronic Test Structures |
| title_sort | proceedings of the 1991 international conference on microelectronic test structures march 18 20 1991 kyoto japan |
| title_sub | March 18 - 20, 1991, Kyoto, Japan |
| topic | Mikroelektronik (DE-588)4039207-7 gnd Prüftechnik (DE-588)4047610-8 gnd |
| topic_facet | Mikroelektronik Prüftechnik Kyōto Konferenzschrift |
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