Digest of technical papers: November 11 - 14, 1991, Santa Clara, California
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. u.a.
IEEE Computer Soc. Press
1991
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XXVIII, 578 S. |
| ISBN: | 0818621575 0818661577 0818691573 |
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| 111 | 2 | |a International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) |n 9 |d 1991 |c Santa Clara, Calif. |j Verfasser |0 (DE-588)5076941-8 |4 aut | |
| 245 | 1 | 0 | |a Digest of technical papers |b November 11 - 14, 1991, Santa Clara, California |c 1991 IEEE International Conference on Computer-Aided Design |
| 264 | 1 | |a Los Alamitos, Calif. u.a. |b IEEE Computer Soc. Press |c 1991 | |
| 300 | |a XXVIII, 578 S. | ||
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Datensatz im Suchindex
| _version_ | 1820868101344854016 |
|---|---|
| adam_text |
Table of Contents
Foreword
.
y
Conference Committee
. . .
vj
Technical Program Committee
.
.vii
Reviewers
. ix
Tutorial: Multi-Level Logic Synthesis
.
й
Tutorial: Advanced Sequential Circuit Testing Techniques
.xii
Tutorial: Software Engineering and Object-Oriented Programming for CAD
.xiii
Tutorial: Framework Technology: Current Status and Future Directions.
. .xiv
Tutorial: CAD and Architecture Issues in FPGAs
.xv
Tutorial: Design, Modeling and Simulation of Multi-Chip Modules
.xvi
Tutorial: CAD Challenges for Consumer Parts and Related Designs
(and) CAD Challenges for Computers and Systems
., . .xvii
Panel Session: The Cutting Edge in CAD: Who Will get the Axe?
.xviii
Acknowledgements
.xix
Sessioni
A: Physical Partitioning
Moderators:
Ulrich Lauîher,
Siemens
AG; Carl Sechen,
Yale University
1A.1
A
Cell-Replicaüng
Abroach to Minicut-Based Circuit Partitioning
. . .2
C. Kring
and
АЛ.
Newton
1A.2 On
Qtering
for Minimum Delay/Area
.6
R. Murgai, R£, Brayton, and A. Sangiovanni-Vincenteltt
1A.3 Fast Spectral Methods for Ratio Cut Partitioning and Clustering
.10
L.
Hagen
and A. Kahng
Session 1B: Analog
Simulation
Moderators:
Karti
Mayaram, Texas Instruments; Rob
Rutenbar,
Carnegie Mellon University
1B.1 iMACSIM: A Program for Multi-Level Analog Circuit Simulation.
. .16
J. Singh and R.
Salek
Щ.2
A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation
. 20
L
M.
Silveira,
J.
White,
and
S.
Leeb
Ш.З
An Accelerated Steady-State Method for Networks with Internally
Controlled Switches
.,.24
D. Bedrosian andJ.
Vlach
Session
IC:
Controller Synthesis
Moderators: Don Thomas, Carnegie MeUon University;
Francky
Catthoor, IMEC Laboratories
ÍC.Í AtttomtócSymliesis
of Time-Statiomry Controllers for Pipelined Data Paths
30
JJ.
Kim,
F J.
Kurdahi,
and
N.
Park
1C.2
layout-Area Models for Higa-Level Synthesis.
. 34
A.C.-H. Wu, V. Chatyakul, andDX). Gajski
1G3 Bffideot Microcode Arrangement and Controller Synthesis for Application
Specific Integrated Circuits
. , 38
S.'Z.IM.C.-T.itwmg.and Y.-C.Hsu
Session 2A: Placement
Moderators: Takeshi Yoshimura, NEC Corporation, Ellen Yoffa, IBM Corporation
2A.1 A New Performance Driven Placement Algorithm
.44
T. Goo, PM. Vakfya, and
СЉ.
Uu
2A.2 RITUAL: Performance Driven Placement Algorithm for Small Cell ICs
.48
A. Srinivasan, K. Chaudhary, and
ES. Kuh
2A.3 Wafer Packing for Fun Mask Exposure Fabrication
.52
C.-T. Wu,
A. Lim,
and
D.
Du
2A.4 A Floorplanning Algorithm Using Rectangular Voronoi Diagram
and Force-Directed Block Shaping
.56
S.-G. Choi and C.-M. Kyung
Session 2B: Interconnect Simulation
Moderators:
Karem
Sakallah,
University of Michigan; Jacob K. White, MIT
2B.
1
An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy
Interconnect Simulation
.62
J.S. Roychowdhury, AM. Newton, and
D.O.
Pederson
2B.2 Delay and Crosstalk Simulation of High-Speed VLSI Interconnects
with Nonlinear Terminations
.66
DM.XUandM.Nakhla
2B.3 Retarded Models for PC Board Interconnects
-
Or How the Speed of Light
Affects your SPICE Circuit Simulation
.70
H.HeebandA.Rmhli
2B.4 Evaluating RC-bitercoimect Using Moment-Matching Approximations
.74
N.
Gopal,
D ľ.
Neikirk, and L.T. Pillage
Session 2C: Scheduling
Moderators: Raul Camposano, GMDIEIS; Alice Parker, University of Southern California
2C.1 The Effects ofFalse Paths in High-Level Synthesis
.80
R
A. Bergamaschi
2C.2 A Scheduling Algorithm for Conditional Resource Sharing.
.84
T. Kim, J.WJ. Uu, and
СЉ.
Uu
2C.3 Optimizing Resource Utilization Using Transformations.
. . 88
M. Potkonjak andJ. Rabaey
2C.4 An Algorithm for Component Selection in Performance Optimized Scheduling
.92
L. Ramachandran and
DJ).
Gajski
Session
ЗА:
Module Generation
Moderators: Youn-Long
Lin, Tsing Hua
University; Wei-Ming Dai,
University
ofCaĘbrnia,
Santa
Cruz
ЗАЛ
Optimal Module Implementation and Its Application to Transistor Placement.
. .98
T.W. Her and
DJ?.
Wong
3AJ2 Track Assignment in the Pamway Datapath Layout Assembler
. 102
AS. Cohen andM. Shechory
3A.3 Flexible Block-Multiplier Generation
. 106
H M
AM. Arts, J.TJ. van Eijndhoven, and
L Stok
XXI
Session
ЗВ:
Numerical Algorithms
Moderators:
Andrzej
Strojwas, Carnegie Mellon University, Ken
Kundért,
Cadence Design Systems
3B.
1
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation:
Algorithms and Applications
.112
K. Mayaram, P. Yang, andJ.-H. Chern
3B.2 Conjugate Direction Waveform Methods for Transient Two-Dimensional
Simulation for
MOS
Devices
.116
A. Lumsdaine.M.
Reichelt,
and
J.
White
3B.3 Transient Sensitivity Computation for Waveform Relaxation Based
Timing Simulation
.120
C J.
Chen,
J.
-M.
Shyu, and
W.
S.
Feng
Session 3C: Topics in Logic Synthesis
Moderators: David Hathaway, IBM; Masahiro Fujita, Fujitsu Labs Ltd.
3d
Heralstic Minimization of Multiple-Valued Relations
.126
Y. Watanabe andRK. Brayton
3C.2 I^AT-An Algorithm for me Synthesis of Two Level Threshold Gate Networks.
. . . 130
AJL.
Oliveira
and A. Sangiovanni-Vincentelli
3C.3 Layout Driven Logic Restroctoring^ecomposition
.134
M. Pedram andN.
В
hat
Session 4A: Real World Framework Applications
Moderators: HitosW Yoshizawa, NEC Electronics; M.Y. Hsueh, Cadence Design Systems
4АЛ
Date Framework for VLSI Design.
.140
A.MÜoandS.Nehab
4AJ2 SLIM: A System for ASIC Library Management
.144
M, Mehendale, P. Murugavel, M. Poornima,
CM.
Nibhanupuã,
and A. Chose
4A.3 Estimating Essential Design Characteristics to Support Project Planning
for ASIC Design Management
. .148
KJ>.
MüUer-Glaser,
К.
Kirsch,
and
К.
Neusinger
4A.4 Ripd-ProiDtYpirjg
of
Haiüwareand
Softwarem a
Unified Framework.
.152
MM. Srtvastma andR.W.
Brödenen
Session 4B: Reliability and Manufacturabillty Analysis
Moderators:
Sarà
Nassif,
ATáTBeU
Labs;
Karti
Mayaram, Texas Instruments
4ВЛ
unproved Methods for
1С
Yi^ »d
(^iality
(^Jtimizatto Usmg Surface mtegrata
. . 158
P. Feldmann and
S.W.
Director
4B.2 New
ЅипнЈаиш
Metods
for
MOS
VLSI Tuning and Reliability
. 162
IM.
ЅМк,
Y, Ubkbici,andS.M. Kong
4B.3
Окяй
Optimization Driven by Worst-Case Distances.
. .166
KJ.AntreíchamíHM.Gmeb
4B.4
QåOTftFfettimaooeVarii^^
od
Practical Solutions
. . . .
ПО
MA.&tyWnManăJ.C.Zhang
XXII
Session 4C: Timing Analysis and Performance Optimization
Moderators: Richard Rudell, Synopsys; Louise Trevillyan, IBM
4C.1 Delay Computation in Combinational Logic Circuits: Theory and Algorithms
.176
5.
Devadas, K. Keutzer, and S. Malik
4C.2 Timing Analysis and Delay-Fault Test Generation Using
Path-Recursive Functions
.180
P.C.
McGeer,
A. Saldanha,
РЯ.
Stephan,
RJC. Brayton,
and
AL. Sangiovanni-Vincentelli
4C.3 Performance Enhancement through the Generalized Bypass Transform
.184
P.C.
McGeer, RJC. Brayton, AJL.
Sangiovanni-Vincentelli,
and S.K.
Sahni
4C.4 Delay Optimization of Combinational Logic Circuits By Clustering
and Partial Collapsing
.188
HJ. Touati, H. Savoj, andRK. Brayton
Session 5A: Diagnostics and Testability Analysis
Moderators: Kent
Fuchs,
University of Illinois·,
Javad Khakbaz,
Tandem Computers
5A.1
DIATEST:
A Fast Diagnostic Test Pattern Generator for Combinational Circuits.
. . 194
T.
Grüning,
U.
Mahlstedt, and H. Koopmeiners
5A.2 Knowledge-Based Debugging of ASICs: Real Case Study
and Performance Analysis
.198
M. MarzoiM andFJL. Vargas
5A.3 BETA: Behavioral Testability Analysis
.,.202
C.-H. Chen,
С
Wu, andD.G. Saab
Session 5B: The False Path Problem in Timing Analysis
Moderators: Michael
Lightner,
University of Colorado; Patrick
С
McGeer, University
of California, Berkeley
5B.1 Pain Sensitization in Critical Path Problem
. 208
H.-C. Chen and DH.C.
Du
5B.2 FPD-An Environment for Exact Timing Analysis
. .212
JJ>.
Suva,
KA. Sakallah,
and
LM. Vidigal
5B.3 A New Approach to Solving False PatnProblem in Timing Analysis
. .216
S.-T. Huang, T.-M. Parng, andJ.-M. Shyu
Session 5C: Encoding Algorithms
Moderators: Giovanni
De Micheli,
Stanford
University,
Raul Camposano, GMDIEIS
5C.
1
State Assignment Based on the Reduced Dependency Theory and Recent
Experimental Results
.222
C. DvffandG. Saucier
5C.2 A Flexible Scheme for State Assignment Based on Characteristics of the
FSM
. 226
B. Mitra, P
Я.
Panda, and
P J'.
Chaudhuri
5C.3 Encoding Multiple Outputs for Improved Column Compaction.
. . .230
D. Binger andD.W.
Knapp
Session 6A: Built-in Self Test
Moderators: Ken Wagner, IBM;
Javad
Khakbaz, Tandem Computers
6АЛ
Synthesis of Optimal 1-Hot Coded On-CMp ControHers for BIST Hardware.
. .236
D. Mukherjee, C. Njtnda, and
M
A.
Breuer
ХХШ
6A.2 BISTSYN-
A Built-in Self-Test Synthesizer
.240
САД.
Chen
6A.3 Comparison of Random Test Vector Generation Strategies
.244
ΨΜ.
Debaty,
Jr.,
СЛЈ*.
Hartmann,
PK.
Varshney, and K.G. Mehrotra
6A.4 Built-in Self-Test for Multi-Port RAMs
.248
V. Castro
Alves,
Af.
Nicolaidis, P.
Lestrat,
and B.
Courtois
Session 6B: Framework Directions
Moderators: Jeff
Bellay,
Texas Instruments', M.Y. Hsueh, Cadence Design Systems
6B.1 The Hercules CAD Task Management System
.254
J.B.
Broekman
and
S.W.
Director
6B.2 The Configuration Management for Version Control in an Object-Oriented
VHDL Design Environment
.258
MJ. Chung and S. Kim
6B.3
SADE:
A Graphical Tool for VHDL-Based System
Analysis
.262
J. Lahti, M. Sipola, andJ.
Rivela
6B.4 System Specification and Synthesis with the SpecCharts Language
.266
S. Narayan, F.
УаШ,
and
DD.
Gajski
Session 6C: Techniques for Effective Memory Utilization
Moderators: Alice Parker, University of Southern California·,
Francky
Catthoor,
IMEC Laboratories
6C.1 Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory
. . .272
/.
Vanhoof, I.
Bolsem,
and H.
De Man
6C.2 Post-Processor for Data
Patta
Synthesis Using
Multipoli
Memories
.276
I. Ahmad and C.YM. Chen
6C.3 austering Techniques for Register Optimization During Scheduling Preprocessing.
.280
F. Depuydt, G. Goossens, andH.
De
Man
6C.4 Scheduling
m
Programmable Video Signal Processors
.284
G. Essink,
E. Aarts,
R.
van
Dongen,
P. van Gerwen,
J.
Korst,
and
К.
Vissers
Session 7A: High-Level Layout
Vérification
Moderators: Antun Domic, Digital Equipment Corporation; Tohra Adachi,
NTTLSI
Laboratońes
7A.1 Circuit Comparison by Hierarchical Pattern Matching
.290
G.
Pelz
and U. Roettcher
7A2 HTVE: An Efficient bterconoect Capacitance Extractor to Support
Submicron
Multilevel Interconnect Designs
.294
KJ. Chang, S.-Y. Oh, andK. Lee
7A.3
ffiearoMeał
Analyser
for VLSI Power Supply Netwoiks Based on a New
Redaction
Metìiod
.298
T.Ymhitome
Session 7B: Timing Analysis
Moderators: Peter Odryna, Precedence,
Іпсл
Kama.
ЅакаШш,
University of Michigan
7В.І
Automatic Detection of
MOS
Synchronizers for Timing Verification
. . .304
J. Grodstdn,
N.
ftetiman, R. Razdm, and G. Bischoff
7B.2 Static Timing
Ащйуш
Using Interval Constrainte
. 308
R.
Stemm
mi J. BmkmM
XXIV
7B.3
ТЪе
Calculation of Signal Stable Ranges in Combinational Circuits
.312
L.-R. Liu, H.-C, Chen, mdDM.C.
Du
Session 7C: Asynchronous Circuit Synthesis
Moderators: Gaetano Borriello, University ofWashington; Teresa
Meng, Stattford
University
7C.1 Automatic Syntiiesis of Locally-Clocked Asynchronous State Machines
.318
SM. Nowick and DJL. Dill
7C.2 Synthesis of Hazaid-Free Asynchronous Circuits firom GrapMcal Specifications,
. . .322
C.W. Moon,
Ρ
Л
Stephan,
andRX. Brayton
7C.3 Synthesis for Testability Techniques for Asynchronous Circuits,
.326
K. Keutzer, L. Lavagno, and A. Sangiovanni-Vincentelli
Session 8A: Performance Driven and Parallel Routing Techniques
Moderators: M. Marek-Sadowska, University of California, Santa Barbara; James Cohoon,
University of Virginia
8A.
1
Timing-Oriented Routers for
PCB
Layout Design of High-Performance Computers
. . 332
Y. Setáyama,
Y.
Fujinara,
T. Hayashi, M.
Seid,
J.
Kusuhara,
К.
lijima, M.
Такакига,
and K. Fukatani
8A.2
Exact Zero Skew
.336
R.-S. Tsay
8A.3 PROTON: A Parallel Detailed Router on an MIMD Parallel Machine
.340
T. Yamauchi, A. Ishizuka, T.
Nakata, N.
Nishiguchi, and
N.
Koike
8A.4 A Parallel
Steiner
Heuristic for Wirelength Estimation of Large Net Populations
. 344
R. JayaramanandRA.
Rutenbar
Session 8B: Topics in Simulation
Moderators: Bill Read,
MCC;
Fabio Somenzi,
University of Colorado
8B.
1
Extraction of Gate Level Models from Transistor Circuits by Four-Valued
Symbolic Analysis
. .350
R E.
Bryant
8B.2 Bipolar Timing Modeling Including Interconnects Based on Parametric Correction
. . 354
A.T. Yang and Y.-H. Chang
8B.3 A Stimulus/Response System Based on Hierarchical Timing Diagrams
.358
K. Khordoc, M. Dvfresne, and E. Cerny
8B.4 Obtaining Functionally Equivalent Simulations using VHDL
and a Time-Shift Transformation
.362
F. Vahid and
DJ).
Gajski
Session 8C: Sequential Synthesis and Verification
Moderators: Robert K. Brayton, University of California, Berkeley, Gary Hacntel,
University of Colorado
8C.1 Ctonvertmg
Cnbinational
Circuits into Pipelined Data Paths
. .368
A.
Münzner
and G.
Hemme
8C.2 An ATPG-Based Approach to Sequential Logic Optimization.
.372
K.-T. Cheng
8C.3 Calculating Resetability and Reset Sequences
.376
C.PixkyandG.Beihl
8C.4 Verification
oŕRelations
Between Synchronous Machines.
. 380
F. Van Aelten, J. Allen, and S. Devadas
xxv
Session 9A: Analog Circuit and Layout
Synthesis
Moderators: Leo Nederlof, Phillips Research Laboratories; Alfred E. Dunlop,
AT&T Bell Laboratories
9A.1 A Behavioral Representation for Nyquist Rate A/D Converters
.386
E. Liu, A. Sangiovanm-VincenteUi, G. Gielen, andP.R. Gray
9A.2 Automating Analog Circuit Design using Constrained Optimization Techniques.
. . .390
P.C.
Maulik andLM. Corky
9A.3 Techniques for Simultaneous Placement and Routing of Custom Analog
Cells in KOAN/ANAGRAM
Π
.394
JM.
Cohn,
DJ.
Garrod,
RA.
Rutenbar,
and
LM.
Carley
Session 9B: Scan Design
Moderators: Shinichi
Murai,
Mitsubishi Electric Corporation; Vishwani D. Agrawal,
AT&T Bell Laboratories
9B.1 A Fault Oriented Partial Scan Design Approach
.400
V. Chickermane andJM.
Patel
9B.2 Timing-Driven Partial Scan
.404
J.-Y.
Jou
and K.-T. Cheng
9B.3 Ordering Storage Elements in a Single Scan Chain
.408
R. Gupta and
ΜΛ.
Breuer
Session 9C: Hlgh-Level Synthesis
-
FSM Synthesis
Moderators: Giovanni
De Micheli,
Starford
University; Gaetano
Bomello,
University
ofWashington
9C.1 Finite State Machine Decomposition by Transition Pairing
.414
/.
Kukuta and S.
Ό
evadas
9C2
Dont
Care Sequences and me Optimization of Interacting Finite State Machines.
. . 418
J.-K. Rho, G. Hachtel, andF. Somenzi
9C.3 An Automatic Finite State Machine Synthesis Using Temporal Logic Decomposition
.422
К. ВеШ,
T.
Nagai,
N.
Hornada,
T.
Shimizu,
N.
Hiratsuka, and
К.
Shirna
Session 10A: Detailed Routing
Moderators:
Snuji
TsuMyama, Chuo University; Chi-Ping Hsu, Cadence Design Systems
10A.1 Algorithms for
Three-IaytrOver-Tbe-Ctìl
Channel Routing
. . 428
NJD. Holmes, NA. Sherwani, andM. Sarrafzadeh
ШК2
A New Model for C^er-The-Cell Channel Routing with Three Layers
. ,432
M. Terai, K. Takahashi, K. Nakajima, and K. Sato
10A-3 A Channel Router for Single Layer Customization Technology.
.436
Y. Sun, S.-K. Dong, S. Sato, and CJU Lm
1ÖA.4
А ШедасМсаі
Methodology to Imprwe Channel Routing by Pin Permutation.
. . .440
CX. Em and CJM. Chen
Session 10B: Automatic Test Pattern Generation
Moderators: Iaeob Abraham, University of Texas; Melvin A.
Breuer,
University
of Southern Caltfornia
10B.1 A New Test Generation Method for Sequential Circuits
. 446
DM. Lee and SM. Ready
ІШ2
Test
Ger^tofijrSyiKdHrao^SequfioiMCSicuits
Based on Fault Extraction.
. .450
I. Pomerom
and SM. Ready
XXVI
10В.З
Increasing Fault Coverage for Synchronous Sequential Circuits
by the Multiple Observation Time Test Strategy
.454
/.
Pomeranz, SM. Ready, andLff. Ready
10B.4 A Signal-Driven Discrete Relaxation Technique for Architectural
Level Test Generation
.,458
J. Lee and
J
Л.
Patel
Session IOC: Verification Algorithms
Moderators: Masahiro Fujita, Fujitsu Labs Ltd;, David Hathaway, IBM
ІОСЛ
Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms.
.464
S.-W. Jeong, B. Plessier, G. Hachtel, andF. Somenzi
10C.2 Probabilistic Design Verification
.468
/.
Jain, J.
Bitner, D.S.
FusseU, and
J
A. Abraham
10C.3 Minimization of Binary Decision Diagrams Based on Exchanges of Variables
. 472
N.
Ishiura, H. Sawada, andS. Yajima
10C.4 Variable Ordering and Selection for FSM Traversal
.476
S.-W. Jeong, B. Plessier, GD. Hachtel, and F. Somenzi
Session
11
A: Transistor-Level Optimization and Layout
Moderators: Rob
Rutenbar,
Carnegie Mellon University; Kazuo Nakajima, Mitsubishi
Electric Corporation
ПАЛ
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits
.482
S.S.
Sapatnekar, VB. Rao, and PM. Vaidya
11A.2 A New Linear Placement Algorithm for Cell Generation
.486
E. Auer, W.
Schiele,
and G.
Sigi
11A.3 Two-Dimensional Layout Synthesis for Large-Scale CMOS Circuits
.490
K.
Tani,
К.
Izvorni,
M.
Kashìmura,
T. Matsuda, and T.
Fujii
Session
11
B: Design
for Testability
Moderators:
Charles
Kime,
University of Wisconsin', Dbiraj K. Pradhan, University of
Massachusetts
11ВЛ
A Systematic Approach for Designing Testable VLSI Circuits
.,.496
S.-P.
Lin, C
A. Njinda, and
M
A.
Breuer
11B.2 Design for Easily Applying Test Vectors to bnprove Delay Fault Coverage,
. ,500
ЕЛ.-М.
Sha
andL.-F.
Chao
11B.3 The Impedance Fault Model and Design for Robust bnpedance Fault Testability.
. .504
MJ). Sloan,
W
A. Rogers, and S. Shoroff
Session 11C: Advances in Combinational Synthesis
Moderators: Gary Hachtel, University of Colorado; David Hathaway, IBM
11СЛ
Application of Boolean Unification to Combinational Logic Synthesis.
.510
M. Fujita, Y. Tanuya, Y. Kukmoto, andK.-C. Chen
11C.2 Extracting Local
Dont
Cares for Network Optimization.
. 514
H. Savoj, RX. Brayton, and HJ.
Tornai
ИС.З
Observability Relations and Observability Don't Cares
.518
H. Savoj and R£. Brayton
XXVII
Session 12A:
Exact Algorithms In General Cell Routing
Moderators:
Jochen A.G.
Jess, Eindhoven University of Tech.; Bryan Preas, XEROX PARC
12A.1 Minimizing Channel Density by Shifting Blocks and Terminals
.524
Y.
Cai
and DF. Wong
12A.2 The Crossing Distribution Problem
. 528
M. Marek-Sadowska andM. Sarrafzadeh
12A.3 On
Topologici Via
Minimization and Routing
.532
M. Hossain andNA, Sherwani
12A.4
Switchbox Steiner
Tree Problem in Presence of Obstacles
.536
■S. Mirtyala, J. Hashnti, andN. Sherwani
Session 12B: Fault Simulation
Moderators: Daniel Saab, University of Illinois; Joseph T. Rahmeh, University of Texas
12B.1 PARIS: A Parallel Pattern Fault Simulator for Synchronous Sequential Circuits.
. . 542
N.
Gouders andR. Kaibel
12B.2 Methods for Reducing Events in Sequential Circuit Fault Simulation.
. 546
EM. Rudmck,
TM. Niermam,
andJH.
Patel
12B.3 Fault Simulation for Multiple Faults Using Shared BDD Representation
of FaultSets
.550
N.
Takahashi,
N.
Ishiura, and S. Yajima
12B.4 A Switch-Level Matrix Approach to Transistor-Level Fault Simulation
.554
T.LeeandlJf.Hajj
Session 12C: Synthesis for FPGA's
Moderators: Kurt Keutzer, Synopsys, Inc.;
Gabriele
Saucier, National
Polytechnique de
Grenoble
12C.1 Multi-Level Logic Minimization Based on Minimal Support and its
Application to the Minimization of Look-Up Table Type FPGAs
. .560
M. Fujita and Y. Matsunaga
12C.2 Improved Logic Synmesis Algorimms for Table Look Up Architectures
.564
R. Murgai,
N.
Shenoy, RJS. Brayton, and A. Sangiovanni-Vincenteltt
12C.3 Technology Mapping of Lookup Table-Based FPGAs for Performance
.568
R J.
Francis,
J.
Rose, and
Z.
Vranesic
12C.4 Performance Directed Synthesis for Table Look Up Programmable Gate Arrays
. . . 572
R. Murgai,
N.
Shenoy,
RM.
Brayton, and A. Sangiovanni-Vincentelli
Author bides
. 576
XXVIII
Author Index
Aarts,E
.284
Abraham,
JA.468
Ahmad,1
.276
Aton,
J.
380
Antreich,
KJ.
166
Arts.rLM.AJM.
.106
Auer.E
.486
Bedrosian,
D
. 24
BeihlG
.376
ВеШ,К.
.422
BenkosM,
J
. 308
Bergamaschi,
R.
Α.
.80
Bhat,N.
.134
Singar,
D.
.230
Bischoff,G
.
304
Bißwa-.J.468
Bolseos, 1
.272
Brayton,RX
.6,126,180,184,188
. . 322,514,518,564,572
Breuer,
MA.
.236,408,496
Brockman,
ЈЈЗ
. . 254
Biotosen, R.W.152
Bryant, RJB.
. 350
Cai,
Y
. . .524
Cariey.LR
.390,394
Ca«ro
Alves»
V.
. 248
Ceray.E
. ,358
ΟΜΒρω,ν.
.34
Cheg.K.-J.
. .294
Chang, Y.-H.
.354
Ομο,Ε,-Ρ.
.500
Ошшйшгу.К.
. ,48
СћаоАш.РЈР.
. 226
Chen.C.-H.
. 202
Chca.C.-IJŁ.
.240
Сћси.СЈ.
120
Cheo.C.YÄ. 276,440
Сћеп.Н.-е.
. .208,312
Сћев.К.-С
. 510
Cheng.K.-T.
.372,404
Сћеш,
J.-a
.112
Шеіюпапе.У.
. .400
СЉм.Ѕ.-О.
. 56
drang,
MJ.
.258
Cotai, AS.
.102
СоЬсШ.
. .394
Courtois.
В
. 248
ШМВП.Н.
. .272,280
Deèeay,
WJŁ,Jr.
. 244
. 280
. 176,380,414
. 318
Director.S.W
.158,254
Dong.S.-K
.436
Da,
DJŁC
.52,208,312
Duff,
С.
222
Dufresne,M
.358
Essink,G
.284
FeMmann,P
.158
Feng, W.S
.120
Francis,
RJ.
568
Fujihara,
Y
.332
Fujii,
T.
.490
Fujita.M.
.510,560
Fukatani,K
.332
Fussell,D.S
.468
Gajski,D.D
.34,92,266,362
Gao,
Τ.
44
GamxLDJ
.394
Gnose, A,
.144
Gielen,G
.386
Goossens, G.
.280
GopaUN.
.74
Gouders,N.
.542
Graeb,IlE
.166
Gray.PJR
.386
Grodstein,
J
.304
Grtaing,T.
. 194
Gupte,R.
.408
Hach»l,GJ>
.
j418.464.476
Hagen,
L.
.10
Над,Ш
. . . . ,554
Hamada,N.
.422
Hartmann,
С
ДЈР.
. . 244
HashmiJ.
.536
Hayashi,T.
. 332
Heeb,H.
.70
Hemme,
G.
. 368
Нет,
T.W
.98
Hiiatsuka.N.
.422
Hohnes.NJD.
.428
Hossain,M.
.532
Hou, C.Y.
. 440
Hsu.Y.-C.
.38
Huang,
ЅЛ1.
.216
Hwang,
C-T
.38
Цјша,К.
.
,
332
lshňira,N.
.
,
.472,550
Шгика, А.
. 340
Izami,
К.
.490
Jain,J
. .468
Jayaranan,
R.
. 344
Jeong.S.-W.
. 464,476
Joö,J.-Y
. 404
576
Kahng, A
.10
Kaibel,R
.542
Kang, S,M
.162
Kashimura,
M
.490
Keutzer.K.
.176,326
Khordoc,
К
.358
Kim,JJ
.30
Kim,
S.
258
Kim,
T.
.84
Kirsch,K
.148
KiveliU
.262
Knapp,
D.W
.230
KoikcN.
.340
Koopmeiners, H
. 194
Korst,
J.
284
Kring, C
.2
К1Ш.Е.Ѕ
.48
Kuldmoto, Y
.510
KukulaJ
.414
Kurdahi,FJ
.30
KusuharaJ
.232
Kyung.C.-M.
.56
Lahti,J
.262
Lavagno,
L
.,.326
Leblebici, Y
.162
LecD-H.
. 446
Lee,J
.458
LecK.
. ,294
Lee, T.
.554
Leeb.S
. .20
Lestrat,P.
.248
Iim,A
.52
lin, S.-P.
.496
Lin, S.-Z
. 38
Ii^CJL
. 44,84,436
Ііи,Е.
.386
1ÍU.J.W.S
. 84
IÍU.L.-R
. 312
Lumsdaine,
Α.
.116
Mahlstedt,U.
. 194
Malik,
S
. 176
Marek-Sadowska.M.
.528
Matzouki,M.
. 198
Matsuda,T.
.490
Matsonaga,
Y.
. 560
ΜβιιϋΙε,Ρ.Ο
. 390
Mayamn,K.
.112
McGeer.P.C
. 180,184
Mehendale,M.
,. 144
Mehrotra,K.G
. .244
Mito, A.
. 140
Miriyala.S.
.536
Mitra,
В
. 226
Мода»
C.W.
. . 322
Miikherjee,D
.236
Müller-Glaser, K.D.148
Münzner,
Α.
368
Murgai,R.6,564,572
Murugavel, P.144
Nagai, T. .422
Nakajima,K.432
Nakata,
Τ
.340
Nakhla,
M
.66
Narayan,
S
.266
Nehab,
S
.140
Neikirk,D.P.74
Neusinger, K. . .148
Newton, AR.2,62
Nibhanupudi.C.M.144
Nicolaidis.M.248
Niermann,
Τ
M.
546
Nishiguchi.N.340
Njinda.C.A.536,496
Nowick, SM.318
Oh, S.-Y. 294
Oliveira,
Ab.130
Panda,P.R. . 226
Parl^N.30
Pamg.T.-M. 216
Patel,
J.H.400,458,546
Pederson, D.0.62
Pedram,M.134
Pelz,
G
. . 290
Pillage,L.T.
. . .74
Pixley.C.376
Plessier.B.464,476
Pomeranz,I. 450,454
Poornima, M. 144
Potkonjak,M.
. 88
Rabaey.J. .88
Ramachandran, L.92
Rao,
УЗ.
482
Razdan,R.304
Reddy,L.N.454
Redáy,
ЅЖ
.446,450,454
Reichelt,
M.
.116
Rethman, N. 304
RhoJ.-K.
.418
Roettcher.U. .290
Rogers, W.A. 504
Rose,
J
. 568
Roychowdhury, J.S
. 62
Rudnick.E.M.546
Rueali, A. . .70
Rutenbar.R.A. 344,394
Saab.D.G.202
Sahni,
S
JL. 184
SakaHah,K.A.
212
577
Saldanha,
A
.180
Sateh,R
.16
Sangiovanni-Vicentelli, A.
. 6,130,180,184,
.326,386,564,572
Sapatnekar, S.S
.482
Sarrafzadeh,M
.428,528
Sato,K
.432
Sato,
S.
436
Saucier, G
.222
Savoj.H,
.188,514,518
Sawada,H.
.472
Schiele,
W
.486
ЅекЦМ.
.332
Sełdyama,
Y
.332
Sha,EÄ-M.500
Shechory,
M
. 102
Shenoy.N.
.564,572
Sherwani,N.A
.428,532,536
Shih, Y.-H.
.162
Shima, K.
.422
Shimizu, T.
.422
Shoroff, S
.504
ShyM.-M.
.120,216
Sigi
G
.486
SilvíUJP.
.212
Silveira,
L.M.
,
. 20
Siagli,
J
.16
Sipo^M.,
. 262
Stom,MJD.
. 504
Someozi,F.
. 418,464,476
Srinivasan, A,
.48
Srivastava.M.B.
.152
Stephan,P.R.
.180,322
Stewart,
R.
. .308
SttđcL.
. 106
StyblinsH, MA.
. 170
Sun, Y
.436
Takahashi,K
.432
Takahashi,N
.550
Takakura,
M
.332
Tamiya,Y
.510
Tani,
K
.490
Terai,M
.432
Touati, HJ
.188,514
Tsay, R.-S
.336
Vahid,F.
.266,362
Vaidya,P.M
.44,482
VanAelten,F.
.380
van Dongen, R
.284
van
Eijndhoven, J.TJ
.106
van
Gerwen, P.
.284
Vanhoof,J
.272
Vargas.FJL
.198
Varshney,P.K
.244
Vidigal.L.M.
.212
Vissers,
K
.284
Vlach,
J
.24
Vranesic, Z
.568
Watanabe.Y
.126
White,
J
.20,116
Wong,DJF.
.98,524
Wu.A.C.-H.
.34
Wu.C.
. .202
Wu, C.-T.
. 52
Xie,
D.H.66
Yajima,S
.472,550
Yamauchi, T
. 340
Yang,A.T.
.354
Yang,P.
.112
Yoshitome, T.
.298
Zhang,
J.C.
.170
578 |
| any_adam_object | 1 |
| author_corporate | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) Santa Clara, Calif |
| author_corporate_role | aut |
| author_facet | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) Santa Clara, Calif |
| author_sort | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) Santa Clara, Calif |
| building | Verbundindex |
| bvnumber | BV005929153 |
| classification_rvk | ZG 9146 |
| classification_tum | ELT 272f ELT 035f |
| ctrlnum | (OCoLC)311677177 (DE-599)BVBBV005929153 |
| discipline | Technik Elektrotechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1991 Santa Clara Calif. gnd-content |
| genre_facet | Konferenzschrift 1991 Santa Clara Calif. |
| id | DE-604.BV005929153 |
| illustrated | Not Illustrated |
| indexdate | 2025-01-10T13:19:01Z |
| institution | BVB |
| institution_GND | (DE-588)5076941-8 |
| isbn | 0818621575 0818661577 0818691573 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-003713028 |
| oclc_num | 311677177 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-739 DE-20 DE-29T DE-83 DE-706 |
| owner_facet | DE-91 DE-BY-TUM DE-739 DE-20 DE-29T DE-83 DE-706 |
| physical | XXVIII, 578 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| publisher | IEEE Computer Soc. Press |
| record_format | marc |
| spelling | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) 9 1991 Santa Clara, Calif. Verfasser (DE-588)5076941-8 aut Digest of technical papers November 11 - 14, 1991, Santa Clara, California 1991 IEEE International Conference on Computer-Aided Design Los Alamitos, Calif. u.a. IEEE Computer Soc. Press 1991 XXVIII, 578 S. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Konsumelektronik (DE-588)4165117-0 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1991 Santa Clara Calif. gnd-content Layout Mikroelektronik (DE-588)4264372-7 s CAD (DE-588)4069794-0 s DE-604 VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s 1\p DE-604 Integrierte Schaltung (DE-588)4027242-4 s 2\p DE-604 Logische Schaltung (DE-588)4131023-8 s 3\p DE-604 Konsumelektronik (DE-588)4165117-0 s 4\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=003713028&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Digest of technical papers November 11 - 14, 1991, Santa Clara, California Logische Schaltung (DE-588)4131023-8 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Konsumelektronik (DE-588)4165117-0 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4131023-8 (DE-588)4027242-4 (DE-588)4264372-7 (DE-588)4165117-0 (DE-588)4121208-3 (DE-588)4117388-0 (DE-588)4069794-0 (DE-588)1071861417 |
| title | Digest of technical papers November 11 - 14, 1991, Santa Clara, California |
| title_auth | Digest of technical papers November 11 - 14, 1991, Santa Clara, California |
| title_exact_search | Digest of technical papers November 11 - 14, 1991, Santa Clara, California |
| title_full | Digest of technical papers November 11 - 14, 1991, Santa Clara, California 1991 IEEE International Conference on Computer-Aided Design |
| title_fullStr | Digest of technical papers November 11 - 14, 1991, Santa Clara, California 1991 IEEE International Conference on Computer-Aided Design |
| title_full_unstemmed | Digest of technical papers November 11 - 14, 1991, Santa Clara, California 1991 IEEE International Conference on Computer-Aided Design |
| title_short | Digest of technical papers |
| title_sort | digest of technical papers november 11 14 1991 santa clara california |
| title_sub | November 11 - 14, 1991, Santa Clara, California |
| topic | Logische Schaltung (DE-588)4131023-8 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Konsumelektronik (DE-588)4165117-0 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Logische Schaltung Integrierte Schaltung Layout Mikroelektronik Konsumelektronik Entwurf VLSI CAD Konferenzschrift 1991 Santa Clara Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=003713028&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT internationalconferenceoncomputeraideddesigninstituteofelectricalandelectronicsengineerssantaclaracalif digestoftechnicalpapersnovember11141991santaclaracalifornia |