Proceedings: Cambridge, Massachusetts, October 14 - 16, 1991
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. u.a.
IEEE Computer Soc. Press
1991
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XVI, 654 S. Ill., graph. Darst. |
| ISBN: | 0818622709 0818622717 0818622725 |
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| 111 | 2 | |a International Conference on Computer Design, VLSI in Computers and Processors |d 1991 |c Cambridge, Mass. |j Verfasser |0 (DE-588)5067473-0 |4 aut | |
| 245 | 1 | 0 | |a Proceedings |b Cambridge, Massachusetts, October 14 - 16, 1991 |c IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| 264 | 1 | |a Los Alamitos, Calif. u.a. |b IEEE Computer Soc. Press |c 1991 | |
| 300 | |a XVI, 654 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
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| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1991 |z Cambridge Mass. |2 gnd-content | |
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Datensatz im Suchindex
| _version_ | 1820868101315493888 |
|---|---|
| adam_text |
Table of Contents
Welcome to ICCD
.
v
Executive Committee
.vi
Technical Program Committee
.
vii
Keynote Session
Chair: E. Middlesworth
*How to Design a Parallel Computer
.2
D. May, Inmos Computer
VLSI Plenary
Chair: J. Van
der
Spiegel
•Liquid Nitrogen CMOS for Computer Applications
.4
F.H. Gaenssien and
D.D.
Meyer, IBM Coqxtration
Architecture Plenary
Chair: B.Ackland
•Neural Networks Update
.10
E.S. Kirkpatrick. IBM Corporation
Design and Test Plenary
Chair: T. Ambler
•Design and Test-The Two Sides of a Coin
.12
V.D. Agrawal AT&T Bell Laboratories
CAD Plenary
Chair: C.
Sechen
•Beyond Logic Synthesis: Open Problems and Challenges for the
90s.
t
G. De
Micheli,
Stanford
University
General Purpose Processors
Chair: W. Dally
Logic Design for a High Performance Mainframe Computer, The
HITAC
M-880 Processor
.14
Y. Shintani, K. Inoue. T. Shonai K.
Wada.
S.
Abe, and
К.
Wakat
Architectural Considerations for SF-core Based Microprocessor
.21
A. Shacham, Y. Levy, Z. Bronstein, E. Loewenstetn,
D.M. Brück,
and D. Deitcher
Symbolic Layout and Module Generation
Chair: J. Bums
Module Generation for AND/XOR Fields (XPLAs)
.26
J. Froessl and B. Eschermann
t(Paper unavailable at press time.)
viii
A
Layout
Compaction Algorithm with
Multiple
Grid Constraints
.30
J.-J. Lee
Methods and Algorithms for Converting
1С
Designs Between
Incompatible Design Systems
.34
E.
Pajeare,
T.
Ritoniemi, and H. Tenhunen
IWLS'9
1 :
Combinational Optimization
Chair: F. Brglez
•Incremental Synthesis for Engineering Changes
.40
Y. Watanabe andRK. Bray ton
Concurrent Resynthesis for Network Optimization
.44
K.-C.
Chen and M. Fujita
♦Dual Global Flow
.49
R.
Damiano
and
L
Berman
Fault Simulation
Chair: T. Ambler
Stafan Algorithms for
MOS
Circuits
.56
J. Villoldo, P. Agrawal and V.D. Agrawal
Fast Differential Fault Simulation by Dynamic Fault Ordering
.60
G. Cabodi S.
Gai
and M. Sonza
Reorda
A Fine Grain Architecture for Parallel Fault Simulation
.64
J. Trotter and R. Evans
IWLS'9
1:
Sequential Optimization
Chair: F. Brglez
Partitioning Sequential Circuits for Logic Optimization
.70
S. Dey, F.
Brglez, and G. Kedem
•Redundancy Identification and Removal Based on Implicit State Enumeration
. 77
H. Cho, CD. Hachtel and F. Somenzt
•Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams
. 81
B. Lin andA.R. Newton
•Retiming of Circuits with Single Phase Transparent Latches
.86
N.
Shenoy, R.K. Brayton, and A.
Sangiovanni-Vtncenteüi
Simulation
Chair:
С
Zukowski
Modeling of Interconnections Lines for Simulation of VLSI Circuits
.92
F.S.G.
dos
Santos andJ.W. Swart
PowerPlay-Fast Dynamic Power Estimation Based on Logic Simulation
.96
Т.Н.
Krodel
Parallel Event-Driven Waveform Relaxation
.101
Y.-C. Wen, K.
Gaüívan,
and R. Saleh
A Technique for Generating Efficient Simulators
.105
P. Bakowski, J.-L·
Dubois,
and
A. Pawlak
IX
Testing Regular Structures
Chair: M.M.E. Aboulhamid
Designing Self-Testable Cellular Arrays
.110
C.-W. Wu and S.-K.
Lu
Concurrent Error Detection In Array Dividers by Alternating Input Data
.114
C.-L Wey
Testing of Analog Neural Array-Processor Chips
.118
W.-J. Hsu, B.J. Sheu, and S.M. Gowda
Fault-Tolerant Model of Neural Computing
.122
L.-C.
Chu
High Performance VLSI Systems
Chair: V. Oktobdzija.
On-Chip Multiple Superscalar Processors with Secondary Cache Memories
.128
M. Hanawa, T. Nishimukai, O. Nishii, M. Suzuki, K. Yano,
M. Hiraki, S. Shukuri, and T. Nishida
•System Level ASIC Design for Hewlett-Packard's Low Cost PA-RISC Workstations
.132
L· Johnson, R. Homing, L. Thayer, D. Li, and R. Snyder
DeslgnFab: A Methodology for ULSI Microprocessor Design
.136
M.Shahaf
•Implementation-Independent Model of an Instruction Set Architecture
Using VHDL
.140
M.H. Salinas,
B.W.
Johnson, andJ.H. Aylor
Panel Session
Chair: B.Ackland
•Fuzzy Logic: Why the U.S. Falls Behind?
.148
GJ.
futr
Monsoon
Chair: Arvind
Overview of the Monsoon Project
.150
K.R. Traub, G.M. Papadopoulos, MJ.
Beckerle,
J.E.
Hicks, and J. Yound
The Monsoon Interconnection Network
.156
C. Joerg and A. Boughton
Test and Validation for Monsoon Processing Elements
.160
M J.
Beckerìe
and
G.M.
Papadopoulos
Routing Algorithms
Chair: R.Tsui
An Effective Analog Approach to
Stelner
Routing
.166
A. Kahng
Performance-Driven Global Routing for Cell Based ICs
.170
J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh, and C.K. Wong
Critical Net Routing
.174
J.P. Cohoon and L· J. Randall
Asynchronous Synthesis
Chair: K. Keutzer
Synthesis of Delay-Insensitive Circuits by Refinements into Atomic Threads
.180
H.F.
Li, S.C.
Leung, and P.N. Lam
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)
.187
M.E. Dean, D.L
DIR,
and M. Horowitz
Synthesis of Asynchronous State Machines Using a Local Clock
.192
S.M. Nowick and D.L. Dill
Delay
Testino
Chair: E.E.P. Hsieh
Amdahl Chip Delay Test System
.200
I. Deol C. Mcdlipeddi, and T. Ramakrishnan
Robust Path Delay-Fault Testability on Dynamic CMOS Circuits
.206
P.C.
McGeer
Syndrome-Based Functional Delay Fault Location in Linear Digital
Data-Flow Graphs
.212
A. Chatterjee and
МЛ.
d'Abreu
Large-scale Multiprocessing
Chair: J. Trotter
A Data-Driven
Architecture for Distributed Parallel Processing
.218
T. Tamara, S.
Komori,
F.
Asai,
H. Tsubota. H.
Sato,
H.
Takata,
Y.
Seguchi,
T.
Tokuda,
and H. Terada
MPU: A N-Tuple Matching Processor
.225
R.H. Payne andJ.G. Delgado-Frias
Transitive Closure and Graph Component Labeling on Realistic Processor
Arrays Based on
Reconfigurable
Mesh Network
.229
M.
Moresca
and P. Baglietto
Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers
.233
H.-C. Chi and Y.
Tornir
Finite State Machine Verification
Chair: L. Claesen
A Compositional Transformation for Formal Verification
.240
E. Cerny
Automatic Derivation of FSM Specification to Implementation Encoding
.245
C. Ptxley, G. BeihL and E. Pacas-Skewes
Design
Vérification
and Reachability Analysis Using Algebraic Manipulation
. . . . 250
S. Devadas, K. Keutzer, and A.S. Krishnakumar
Boolean Satisfiability and Equivalence Checking Using General
Binary Decision Diagrams
.259
P. Ashar, A. Ghosh and S. Devadas
Built-In Self Test
Chair: A.Albicki
Power-Down Structures for BIST
.266
P.S.
Levy
Xl
A Unique Approach to Built-in-Self-Test Circuit Design
.270
SA. Al-Arian,
H.Y. Abujbara, andJ.C. Ruel
New Implementations, Tools, and Experiments for Decreasing Self-Checking
PLAs Area Overhead
.275
M. Nicolaidis and M.
BoudJÜ
A Built-in Self-Testing Approach for Minimizing Hardware Overhead
.282
S.S.K.
Chiu
and CA. Papachrtstou
High Speed Processor Technologies
Chair: K.-M. Cham
•CMOS Processor Circuit Design in Hewlett-Packard's Series
700
Workstations
. . 288
C. Gleason.
M. Forsyth,
С.
Kohlhardt,
S.
Mangelsdorf,
B. Arnold, and R.
Luebs
F-RISC/I: Fast Reduced Instruction Set Computer with GaAs
(H)MESFET Implementation
.293
C.K.
Tien, C.C. Poon,
H.
Greub, and J.
F. McDonald
F-RISC/G: AlGaAs/GaAs HBT Standard
Cell
Library.297
К
Nah, R. Philhower, J.S. Van Etten, S.
Simmons, V.
Tstnker,
J. Loy, H. Greub, and J.F. McDonald
A Mechanism for Efficient Context Switching
.301
P.R. Nuth and WJ. Daily
Floorplanning I
Chair: C.
Sechen
A Genetic Algorithm for Global Improvement of Macrocell Layouts
.306
K.
Glasmacher,
A. Hess, and G.
Zimmermann
I/O Pad Assignment Based on the Circuit Structure
.314
M.
Pearam,
K. Chaudhary, and E.S.
Kuh
A Provable Near-Optimal Algorithm for the Channel
Pln
Assignment Problem
. . . .319
J. Cong and K.-Y. Khoo
MIPS
Chair: C.
Sechen
Design Methodology for a MIPS Compatible Embedded Control Processor
.324
R. Peck and J.
Patel
Verification Techniques for a MIPS Compatible Embedded Control Processor
. 329
D. Jones, R. Yang, M. Kwong, and G. Harper
The Architecture of the LR33000: A MIPS Compatible RISC Processor for
Embedded Control Applications
.333
B. Caulk, S. Desai, M. Gavrielov, G. Harper, D. Jones, M. Kwong,
M. Murzello,
Т. Оке,
J.
Patel
R.
Peck, J. Wei, and R.
Yang
Pormal
Verification and Synthesis
Chair:
К.
Keutzer
Illustration of the SFG-Tracing Multi-Level Behavioral Verification
Methodology, by the Correctness Proof of a High to Low Level Synthesis
Application In CATHEDRAL-II
.338
M. Genoe, L· Claesen, E. Verlind, F. Proesmans. and H.
De Man
Specifying System Behavior in
CPA
.342
M.C. McFaňand
and
TJ.
Kowalski
Xli
A Formally Verified System for Logic Synthesis
.346
M. Aagaard and M. Leeser
Signature Analysis and Aliasing
Chair: N.K.Jha
Aliasing Probability in Multiple Input Linear Signature Automata for
Q-ary Symmetric Errors
.352
G. Edirisooriya and J.P. Robinson
Reduced Hamming Count and Its Aliasing Probability
.356
A. Gleason and W.-B.
Jone
On the Manisfestation of Faults to Errors in Signature Analysis
.360
J.C. Chan, B.F. Womack, andD.F. Wong
Symbolic Processing
Chair: G. Saucier
Operation Method in Fuzzy Set Operation Processor
.366
A. Katsumata, H. Tokunaga, and S. Yasunobu
A Tag Coprocessor Architecture for Symbolic Languages
.370
V. Fuentes-Sanchez and P.Y.K. Cheung
An Efficient Pattern Match Architecture for Production Systems Using
Content-Addressable Memory
.374
C.
Dou
and S.-M. Wu
Object-Caching for Performance in Object-Oriented Systems
. . 379
J.M. Chang and E.F. Gehringer
Performance Enhancment
Chair: B. ColweU.
Early Performance Estimation of Super Scalar Machine Models
.388
P.
Bose
Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter
. 393
S. Karthik, I.
de Souza,
J.T.
Rahmen,
апаЈЛ.
Abraham
An Adaptive
Hardware
Machine Architecture and Compiler for
Dynamic Processor Reconfiguration
.397
P.M.
Athanas and H.F.
Silverman
FASTCHART-Idea and Implementation
.401
L·
Ltndh
and F. Stanischewski
High Level Synthesis
Chair:
M. McFaňand
Mapping Design Knowledge from Multiple Representations
.406
W.Cyre
Synthesizing Converters Between Finite State Protocols
.410
J. AkeUa and K. McMillan
An Integrated Design Environment for Application Specific Integrated Processor
. .414
J. Sato, M. Imai, T.
Hakata,
AY. Alomary, and
N.
Hikichi
Allocation of Multiport Memory with Ports of Different Type in Register
Transfer Level Synthesis
.418
C.-I.H.
Chen
Kill
Redundancy Issues
Chair: S. Ghosh
Random Testability of Redundant Circuits
.424
A. KrasniewskiandA. Albicki
Logic Synthesis of lOO-percent Testable Logic Networks
.428
G.-J.
Tromp
andA.J. van
de Goor
Fault Tolerant VLSI Design with Functional Block Redundancy
.432
R. Ernst and P. Nowottnick
ICCD Banquet
Chair: E. Middlesworth
♦Design and Test Automation-Gigascale Integration (GSI) in the 21st Century
. . . 438
J.D. Meindl Rensselaer Polytechnic Institute
AS
400
Chair: A. Berenbaum
IBM
AS/400
Processor Architecture and Design Methodology
.440
Q.G.
Schmierer
and A.H. Wottreng
VLSI Design Automation for the Application System/400
.444
R.F. Lembach, J.M.
Borkenhagen, J.R.
Elliott, and
RЛ.
Schmidt
IBM
AS/400
Processor Technology
.448
D.T. Cox, C.L· Johnson, B.G.
Rudolph, D.W. SÜjenberg, andR.R.
WUliams
Design and Test Automation
Chair: A. Albicki
Logic Synthesis of Synchronous Parallel Controllers
.454
J. Pardey and M.
Bolton
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability
.458
C. Papachristou, S.
Chiu,
and H. Harmanani
Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability
.463
C.-H. Chen,
С
Wu, andD.G. Saab
Interconnect and Packaging
Chair: T. Lgszczarz
Fine-Line Printed Circuit Board for High-Performance Computer Design
.468
C.-C. Huang, J. Willis, and T.
Schmitt
Design Considerations for Digital Circuit Interconnections in a Multilayer
Printed Circuit Board
.472
A.P. Agrawal C.S. Chang, and
ΩΛ.
Gernhart
Fast Capacitance Extraction of General Three-Dimensional Structures
.479
К
Nabors, S. Kim, J. White, and S. Senturia
Optical Computing
Chair: S. Tewksbwy
A Simulator for General Purpose Optical Arrays
.486
W.B. Marvin and W.P. Burleson
•An Optical Multichip Module
.490
A. Dickinson and MM. Downs
XIV
A GaAs Receiver Module for Optoelectronic Computing and Interconnection
.494
J. Choi and BJ. Sheu
Special Purpose VLSI Architectures
Chair: A. Dahbura
VLSI Designs for High-Speed Huffman Decoder
.500
S.-F. Chang andD.G.
Messerschmitt
BioSCAN: A VLSI-Based System for Biosequence Analysis
.504
C.T. White, R.K. Singh, P.B. Reintjes, J.
Lampe.
B.W.
Erickson, W.D.
DetÜoff. V.L.
Chi, and
S.F.
Altschul
VLSI Implementation of a New Block Cipher
.510
H. Bonneriberg, A. Curiger,
N.
Felber, H. Kaesltn, and X. Lai
Nimbus: An Integrated Display Chip
.514
B. Locanthi and R. McLellan
Floorplanning
Π
Chair: G.
Zimmermann
An Optimal Algorithm for Spiral Floorplan Designs
.516
C.-H. Chen and I.G. Tollis
Area Optimization for Higher Order Hierarchical Floorplans
.520
K.-S. The and D.F. Wong
The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified
Algorithm for Feasible Routing Order
.524
S. Sur-Kolay and B.B. Bhattacharya
Flipping Modules to Minimize Maximum Wire Length
.528
K. Chang and S.
Sahni
ЮМ
ES/9000™ VLSI
Chair;
S.
DasGupta
High Performance Packaged Electronics for the IBM ES9000™ Mainframe
.534
A. Barish, J.
Eckhardt,
M.
Mayo,
W.
Svarczkopf, S.
Gaur,
and R.
Tummála
IBM ES/9000™ System
Architecture
and Hardware.540
WJ. Nohiüy and V.T.
Lund
Enhanced Chip/Package
Design
for the IBM ES/9000™
.544
R.S.
Bélanger,
D.P. Conrady,
P.S.
Honstnger, TJ. Lavery,
SJ.
Rothmann,
E.C.
Schanzenbach,
D. Sitaram,
CR. Selinger,
R.E. DuBots, G.W. Mahoney, and G.F.
Miceli
Design
Automation
of Test for the ES/9000™ Series Processors
.550
B.L. Keller and DA. Haynes
Computer Arithmetic
Chair: P.
Cappello
A Comparison of Redundant CORDIC Rotation Engines
.556
JA.
Harding, T. Lang, andJ.-A. Lee
A Fast Division Algorithm for VLSI
.560
N.
Burgess
High-Speed VLSI Arithmetic Processor Architectures Using
Hybrid Number Representation
.564
H.R. Srinivas and K.K. Parhi
XV
Error Checking Schemes
Chair: K. Wagner
New Classes of Unidirectional Error-Detecting Codes
.574
B. Parhami
Design and Synthesis of Self-Checking VLSI Circuits and Systems
.578
N.K. Jha and S.-J. Wang
Design of a Self-Testing Checker for
Borden
Code
.582
SJ. Piestrak
Multichip Modules
Chair: R.S. Iyer
•Technologies for Rapid Prototyping of Multi-Chip Modules
.588
R. Miracky, T. Bishop, C. Galanakts, H. Hashemi, T.
Hirsch,
S. Madère, H.
Мйиег,
T. Rudwick,
L. Smith,
S. Sommerfeldt, and B. Weigler
•Energy
Considerations in Multichip-Module Based Multiprocessors.
593
J.B.
Burr and AM. Peterson
•The Commercial Realization of Multi-Chip Modules Quo Vadimus
.601
R.
Hendel
Numeric Processing
Chair: B.J. Sheu
High-Performance VLSI Processor for Robot Inverse Dynamics Computation
. ,608
S. Kittichaikoonkit, M. Kameyama, and T. Higuchi
A New 0{n log n) Scheduling Heuristic for Parallel Decomposition of
Sparse Matrices
.612
R. Telichevesky, P. Agrawal and J.A. Trotter
A Predictive Parallel Motion Estimation Algorithm for Digital Image Processing
. . .617
L-G. Chen, W.-T. Chen, Y.-S. Jehng, and T.-D. Chiueh
A Multiprocessor Architecture for Circuit Simulation
.621
J. Trotter and P. Agrawal
Random Thoughts
m
Logic Synthesis
Chair: C.
Sechen
Three-Level Decomposition with Application to PLDs
.628
АЛ.
Malik. D. Harrison, and R.K. Brayton
An Algorithm for the Multi-Level Minimization of Reed-Muller Representations
. . . 634
J.Said
Identification of Viable Paths Using Binary Decision Diagrams
.638
Y.-C.JuandRA.Saleh
Optimal Clocking of Circular Pipelines
.642
КЛ.
SakaUah, T.N. Mudge, T.M. Burks, and E.S. Davidson
Author Index
.651
Note: Papers marked
" ♦ "
are invited.
XVI
Author Index
Aagaard,
M
.346
Abe,
S
.14
Abraham,
J
.A.
.393
Abujbara, H.Y
.270
Agrawal. A.P
.472
Agrawal.
Ρ
.56, 612, 621
Agrawal, V.D
.12, 56
Akella,
J
.410
Al-Arlan,
S.A.270
Albicki. A.
.,424
Alomary,
Α. Υ
.414
Altschul,
S.F
.504
Arnold,
В
.288
Asai,
F
.218
Ashar,
P
.259
Athanas,
P.M
.397
Aylor,
J.H
.140
Baglletto,
P
.229
Bakowskl,
P
.105
Barish,
Α.
.534
Beckerle, M.J.150, 160
Belhl,
G.
245
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| any_adam_object | 1 |
| author_corporate | International Conference on Computer Design, VLSI in Computers and Processors Cambridge, Mass |
| author_corporate_role | aut |
| author_facet | International Conference on Computer Design, VLSI in Computers and Processors Cambridge, Mass |
| author_sort | International Conference on Computer Design, VLSI in Computers and Processors Cambridge, Mass |
| building | Verbundindex |
| bvnumber | BV005928679 |
| classification_rvk | ST 150 |
| classification_tum | ELT 272f DAT 210f DAT 190f |
| ctrlnum | (OCoLC)256216799 (DE-599)BVBBV005928679 |
| discipline | Informatik Elektrotechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1991 Cambridge Mass. gnd-content |
| genre_facet | Konferenzschrift 1991 Cambridge Mass. |
| id | DE-604.BV005928679 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:19:01Z |
| institution | BVB |
| institution_GND | (DE-588)5067473-0 |
| isbn | 0818622709 0818622717 0818622725 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-003712649 |
| oclc_num | 256216799 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-739 DE-634 DE-83 DE-706 |
| owner_facet | DE-91 DE-BY-TUM DE-739 DE-634 DE-83 DE-706 |
| physical | XVI, 654 S. Ill., graph. Darst. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| publisher | IEEE Computer Soc. Press |
| record_format | marc |
| spelling | International Conference on Computer Design, VLSI in Computers and Processors 1991 Cambridge, Mass. Verfasser (DE-588)5067473-0 aut Proceedings Cambridge, Massachusetts, October 14 - 16, 1991 IEEE International Conference on Computer Design: VLSI in Computers and Processors Los Alamitos, Calif. u.a. IEEE Computer Soc. Press 1991 XVI, 654 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Prozessor (DE-588)4176076-1 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1991 Cambridge Mass. gnd-content Prozessor (DE-588)4176076-1 s VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s DE-604 CAD (DE-588)4069794-0 s Computerarchitektur (DE-588)4048717-9 s 1\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=003712649&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings Cambridge, Massachusetts, October 14 - 16, 1991 Computerarchitektur (DE-588)4048717-9 gnd Entwurf (DE-588)4121208-3 gnd Prozessor (DE-588)4176076-1 gnd CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4048717-9 (DE-588)4121208-3 (DE-588)4176076-1 (DE-588)4069794-0 (DE-588)4117388-0 (DE-588)1071861417 |
| title | Proceedings Cambridge, Massachusetts, October 14 - 16, 1991 |
| title_auth | Proceedings Cambridge, Massachusetts, October 14 - 16, 1991 |
| title_exact_search | Proceedings Cambridge, Massachusetts, October 14 - 16, 1991 |
| title_full | Proceedings Cambridge, Massachusetts, October 14 - 16, 1991 IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| title_fullStr | Proceedings Cambridge, Massachusetts, October 14 - 16, 1991 IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| title_full_unstemmed | Proceedings Cambridge, Massachusetts, October 14 - 16, 1991 IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| title_short | Proceedings |
| title_sort | proceedings cambridge massachusetts october 14 16 1991 |
| title_sub | Cambridge, Massachusetts, October 14 - 16, 1991 |
| topic | Computerarchitektur (DE-588)4048717-9 gnd Entwurf (DE-588)4121208-3 gnd Prozessor (DE-588)4176076-1 gnd CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Computerarchitektur Entwurf Prozessor CAD VLSI Konferenzschrift 1991 Cambridge Mass. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=003712649&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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