Proceedings 1991: June 17 - 21, 1991 San Francisco, California, Moscone Center
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| Format: | Tagungsbericht Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
New York, NY
Assoc. for Computing Machinery
1991
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XXIII, 783 S. graph. Darst. |
| ISBN: | 0897913957 0818691492 0818661496 |
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| 111 | 2 | |a Design Automation Conference (Association for Computing Machinery) |n 28 |d 1991 |c San Francisco, Calif. |j Verfasser |0 (DE-588)5065346-5 |4 aut | |
| 245 | 1 | 0 | |a Proceedings 1991 |b June 17 - 21, 1991 San Francisco, California, Moscone Center |c 28th ACM/IEEE Design Automation Conference ; [general chair A. Richard Newton] |
| 264 | 1 | |a New York, NY |b Assoc. for Computing Machinery |c 1991 | |
| 300 | |a XXIII, 783 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
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Datensatz im Suchindex
| _version_ | 1804120114990153728 |
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| adam_text | TABLE
OF
CONTENTS
1991
KEYNOTE ADDRESS
.............................................................................................................1
Joseph
В.
Costello
Session
1 :
Application of Mixed Integer Linear Programming to High-Level Synthesis
(Chair: M. McFarland, SJ; Organizers: E. Girczyz, M. McFarland, SJ)
1.1
Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis
............................2
Catherine H. Gebotys and
Mohamed
I. Elmasry
1.2
Synthesis of Application-Specific Multiprocessor Architectures
..............................................................................8
Shiv Prakash and Alice C. Parker
1.3
Constraint Improvements for MILP-Based Hardware Synthesis
.............................................................................14
Lou
Hafer
Session
2:
Circuit and Timing Simulation
(Chair: R. Saleh; Organizers: R. Saleh, A. Strojwas)
2.1
ILLIADS: A New Fast
MOS
Timing Simulator Using Direct Equation-Solving Approach
..................................20
Y.-H. Shih and S. M. Kang
*2.2 ADAPTS: A Digital Transient Simulation Strategy for Integrated Circuits
............................................................26
Alexander D. Stein, Tuyen V. Nguyen, Binay J. George and Ronald A. Rohrer
2.3
Efficient Simulation of Bipolar Digital ICs
.............................................................................................................32
Chandramouli Visweswariah and Ronald A. Rohrer
Session
3:
PANEL:
Global Strategies for Electronic Design
(Chair: H. Jones; Organizer: D. Wanat)
Panel Members: Thomas Bruggere, Wilfred
Corrigan,
Joseph
Costello,
John East, Susumu Kohyama, Edward McCracken
.................................................................................................38
Session
4:
Multi-Layer Area Routing
(Chair: U. Lauther; Organizers: U. Lauther, K. Hirakawa)
4.1
Topological Routing in SURF: Generating a Rubber-Band Sketch
........................................................................39
Wayne Wei-Ming Dai,
Tal Dayan
and David Staepelaere
4.2
Routability of a Rubber-Band Sketch
......................................................................................................................45
Wayne Wei-Ming Dai, Raymond Kong and Masao Sato
4.3
Novel Routing Schemes for
1С
Layout Part I: Two-Layer Channel Routing
..........................................................49
Deborah C. Wang
4.4
A New Hypergraph Based Rip-Up and Reroute Strategy
........................................................................................54
Manuela
Raith and Marc Bartholomeus
4.5
Constrained Via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems
......60
Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, and
Sao
-Ле
Chen
Session
5:
Synthesis and Delay Testing
(Chair: K. Keutzer; Organizers: K. T. Cheng, T. W. Williams)
5.1
Logic Synthesis For Efficient
Pseudoexhaustive
Testability
...................................................................................66
Andrzej
Krasniewski
5.2
Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage
...........................................................73
Weiwei Mao and Michael D.
Cileni
*Best Paper Award Candidates
xv
5.3 Robust
Delay-Fault
Test Generation
and Synthesis for Testability Under A
Standard Scan Design Methodology
........................................................................................................................80
Kwang-Ting Cheng, Srinivas Devadas and Kurt Keutzer
*5.4 The Interdependence Between Delay-Optimization of Synthesized Networks and Testing
...................................87
T. W. Williams, Bill Underwood and M. R. Mercer
Session
6:
Technology Mapping
(Chair: R. Rudell; Organizers: M.
Lightner,
A. Sangiovanni-Vincentelli)
6.1
A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings
.................................................93
M. Crastes, K. Sakouti and
G. Saucier
*6.2 Layout Driven Technology Mapping
.......................................................................................................................99
Massoud Pedram and Narasimha Bhat
6.3
An ECL Logic Synthesis System
...........................................................................................................................106
Van Morgan and David Gregory
6.4
Timing Optimization on Mapped Circuits
.............................................................................................................112
Ko
Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Sigenobu Suzuki, Nobuyoshi Nomizu and Akira Kondoh
Session
7:
Design Automation in the Soviet Union: History and Status
(Chair: E. Horbst; Organizer: A. R. Newton)
Presenter: Gennady G. Kazyonnov
........................................................................................................................118
Session
8:
PANEL:
Implementing the Vision: Electronic Design in the 1990 s
(Chair:
A. Rappaport;
Organizer: D. Wanat)
Panel Members: Andy Bechtolscheim, John
Darringer,
Aart de Geus, Satoshi Goto,
Alain Hanover,
Egon
Horbst, Gennady Kazyonnov
..............................................................................................119
Session
9:
Over the Cell Channel
Routing
(Chair: F. M.
Johannes; Organizer: U. Lauther)
*9.1 Channel
Density Reduction By
Routing
Over The Cells.......................................................................................
120
Min-Siang
Lin,
Hourng-Wem Perng, Chi-Y i
Hwang and Youn-Long Lin
9.2
New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals
.....................................................126
Nancy D. Holmes, NaveedA. Sherwani and Majid Sarrafzadeh
9.3
Routing the
3-D
Chip
.............................................................................................................................................132
Richard J. Enbody, Gary Lynn and
Kwee Heong
Tan
Session
10:
Fault Simulation
(Chair: E. Uriche; Organizers: K. T. Cheng,
T. W.
Williams)
10.1
Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation
...............................................................138
E. Vandris and
G. Sobelman
10.2
A System for Fault Diagnosis and Simulation of VHDL Descriptions
.................................................................144
Vijay Pitchumani, Pankaj Mayor and Nimish
Radia
10.3
Sequential Circuit Fault Simulation by Fault Information Tracing Algorithm: FIT
..............................................151
Yoshihiro Kitamura
10.4
Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors
........................................155
Srinivas
Patii,
Prithviraj Banerjee and Janak H.
Patel
10.5
Creator. General and Efficient Multilevel Concurrent Fault Simulation
...............................................................160
P. L. Montessoro and S.
Gai
*Best Paper A ward Candidates
xvi
Session 11 :
Sequential Synthesis
(Chair:
S.
Malik; Organizers: M.
Lightner,
A. Sangiovanni-Vincentelli)
11.1
On Removing Redundancy in Sequential Circuits
.................................................................................................164
Kwang-Ting Cheng
11.2
A Framework for Satisfying Input and Output Encoding Constraints
...................................................................170
Alexander
Saldanha,
Tiziano Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli
11.3
A Unified Approach to Input-Output Encoding forFSM State Assignment
.........................................................176
Maciej
J.
Ciesielski,
Jia-Jye Shen and Marc
Davio
11.4
FSM Decomposition Revisited: Algebraic Structure Theory Applied to MCNC Benchmark FSMs
...................182
Martin
Geiger
and Thomas
Mülle
r-Wipperfiirth
Session
12:
PANEL:
Intellectual Property
(Chair: M. McFarland, SJ)
Panel Members: Daniel
Appelman, Srinivas Devadas, Aart de Geus
...................................................................186
Session
13:
Leading-Edge Design Systems
(Chair: T. Kozawa; Organizers: D. Hill, E. Yoffa)
13.1
A CAD System for the Design of Field Programmable Gate Arrays
....................................................................187
Dwight D. Hill
* 13.2
Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers
..............193
Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kogawa, Mitsugu Edagawa,
Satoshi Hososaka and Masahiro Hashimoto
* 13.3
SIDECAR Design Support for Reliability
.............................................................................................................199
Charles R. Yount and Daniel P. Siewiorek
Session
14:
Improving Simulator Performance
(Chair: P. M.
Maurer;
Organizers: R. Bryant, R. Saleh)
1
4.
1 Automatic Generation of Compiled Simulations through Program Specialization
...............................................205
Wing Yee
Au,
Daniel
Weise
and Scott Seligman
14.2 Accelerating Switch-Level Simulation by Function Caching
................................................................................211
Larry G. Jones
14.3
Utilizing Logic Information in Multi-Level Timing Simulation
...........................................................................215
Marko
P. Chew and
Andrzej
J
.
Strojwas
14.4
Mapping switch-level simulation onto gate-level hardware accelerators
..............................................................219
Alok Jain and Randal E. Bryant
14.5
Breaking the Barrier of Parallel Simulation of Digital Systems
............................................................................223
Jack V.
В
rine
r, Jr., John L. Ellis and
Ger shon Kedem
Session
15:
Synthesis for Programmable Gate Arrays
(Chair: A. EIGamal; Organizers: M.
Lightner,
A. Sangiovanni-Vincentelli)
15.1
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs
.............................................................227
Robert Francis, Jonathan Rose and
Zvonko Vranesic
15.2
Technology Mapping for Electrically Programmable Gate Arrays
.......................................................................234
Silvia Ercolani and Giovanni
De Micheli
15.3
Xmap: A Technology Mapper for Table-lookup Field-Programmable Gate Arrays
.............................................240
Kevin Karplus
15.4
Amap: A Technology Mapper for Selector-based Field-Programmable Gate Arrays
...........................................244
Kevin Karplus
15.5
A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility
............................................248
Nam-Sung Woo
*Best Paper Award Candidates
xvii
Session 16: PANEL:
What is
Design
for
Manufacturability (DFM)?
(Chair:
W. Mały)
Panel Members: P. Chatterjee, W. R. Griffin, J.
Grupp,
J.
Plummer,
S. Tewksbury, P.
Verhofstadt
...................252
Session
17:
Layout
Systems
(Chair:
E.
Yoffa;
Organizers:
R.
Rutenbar,
E. Yoffa)
17.1
Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design
...............................253
Yasushi Ogawa, Tsutomu ltoh, Yoshio
Miki, Tatsuki
Ishii, Yasuo Sato and
Reiß Toyoshima
17.2
Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing System
.....................259
Christian Masson,
Remy Escassut,
Denis
Barbier,
Daniel Winer and Gregory
Chevallier
17.3
Benchmarks for Layout Synthesis
—
Evolution and Current Status
.......................................................................265
Krzysztof Koźminski
Session
18:
Design for Testability and Built In Self Test
(Chair: T. W. Williams; Organizers: K. T. Cheng,
T. W.
Williams)
18.1
A Design for Testability Scheme with Applications to Data Path Synthesis
.........................................................271
Scott
Chiu
and
Christos
A. Papachristou
18.2
Enhanced Controllability for IDDQTest Sets Using Partial Scan
............................................................................278
Tapan
J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga and
C.
J. Lin
18.3
ATPG Based on a Novel Grid-Addressable Latch Element
..................................................................................282
Susheel J. Chandra, Tom Ferry, Tushar Gheewala and Kerry Pierce
18.4
Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit
....................................................................287
Chien-ln Henry Chen
18.5
Delay Test Effectiveness Evaluation of LSSD-Based VLSI Logic Circuits
..........................................................291
David M. Wu and Charles E. Radke
Session
19:
Synthesis of Asynchronous Circuits
(Chair:
T. Chu;
Organizers: M.
Lightner,
A. Sangiovanni-Vincentelli)
19.1
Automatic Synthesis of Asynchronous Circuits
....................................................................................................296
Kuan-Jen Lin and Chen-Shang Lin
и
19.2
Algorithms for synthesis of hazard-free asynchronous circuits
.............................................................................302
L
Lavagna,
К.
Keutzer and A. Sangiovanni-Vincentelli
19.3
Synthesis of Multiple-Input Change Asynchronous Finite State Machines
..........................................................309
Maureen Ladd and William P. Birmingham
Session
20:
PANEL:
Framework Standards: How important Are They?
(Chair: A. R. Newton; Organizer: D. Wanat)
Panel Members: Jayaram Baht, Matt Goldstein, Andy Graham, Takahide Inoue,
Thanasis Kalekos,
Bernd Steinmüller,
Drew Wade, Mitch Weaver
......................................................................315
Session
21 :
Global Considerations in Routing
(Chair: G. Saucier; Organizer: U. Lauther)
21.1
A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm
.................316
Robert C.
Carden
IV and Chung-Kuan Cheng
21.2
High-Performance Clock Routing Based on Recursive Geometric Matching
.......................................................322
Andrew Kahng, Jason Cong, and Gabriel Robins
*Best Paper Award Candidates
xviii
21.3
On Minimizing the Number of L-Shaped Channels
..............................................................................................328
Yang
Cai
and D. F. Wong
21.4
A General Multi-Layer Area Router
......................................................................................................................335
Mohankumar Guruswamy and D. F. Wong
Session
22:
Test Pattern Generation
(Chair: K. T. Cheng; Organizers: K. T. Cheng, T. W. Williams)
22.1
On Achieving A Complete Fault Coverage for Sequential Machines Using the Transition Fault Model
.............341
Irith Pomeranz and Sudhakar M. Ready
22.2
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-Level Circuits
........347
Stephen
Pateras
and
Janusz Rajski
22.3
A Transitive Closure Based Algorithm for Test Generation
..................................................................................353
Srimat T. Chakradhar and Vishwani D. Agrawal
22.4
A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults
.................................................359
Srinivas Devadas, Kurt Keutzer and Sharad Malik
Session
23:
Datapath and Control Synthesis
(Chair: M.
Lightner;
Organizers: G.
De Micheli,
M.
Lightner)
*23.1
Control Optimization Based on Resynchronization of Operations
........................................................................366
David
C. Ku,
Dave
Filo
and Giovanni
De Micheli
23.2
A Unified Approach for the Synthesis of Self-Testable Finite State Machines
.....................................................372
Bernhard Eschermann
and
Hans-Joachim Wunderlich
23.3
A Data Path Synthesis Method for Self-Testable Designs
.....................................................................................378
Christos
A. Papachristou, Scott
Chiu
and Haidar Harmanani
23.4
Automated Micro-Roll-Back Self-Recovery Synthesis
.........................................................................................385
Vijay Raghavendra and Chidchanok Lursinsap
Session
24:
Formal Design Verification
(Chair: J.
С
Madre;
Organizers:
R.
Bryant, A. Sangiovanni-Vincentelli)
24.1
Proof-Aided Design of Verified Hardware
............................................................................................................391
Holger Busch
and
Gerd Venzl
24.2
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation
........................................................397
Randal E. Bryant, Derek L. Beatty and
Carl-Johan
H.
Seger
24.3
Representing Circuits More Efficiently in Symbolic Model Checking
.................................................................403
J. R. Burch, E. M. Clarke and
D. E.
Long
24.4
Using BDDs to Verify Multipliers
.........................................................................................................................408
Jerry R. Burch
24.5
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing
.............................................413
Hiroyuki
Ochi,
Nagisa
Ishiura and Shuzo Yajima
24.6
Heuristics to Compute Variable
Orderings
for Efficient Manipulation of Ordered Binary Decision Diagrams...417
Kenneth M. Butler, Don E. Ross, Rohit Kapur and M. Ray Mercer
Session
25:
Partitioning and Placement
(Chair: C.
Sechen;
Organizers: B. Preas, R.
Rutenbar)
*25.1 A General Purpose Multiple Way Partitioning Algorithm
.....................................................................................421
Ching- Wei Yeh, Chung-Kuan Cheng and Ting-Ting Y. Lin
* 25.2
Analytical Placement: A Linear or a Quadratic Objective Function?
....................................................................427
Georg Sigi,
Konrad
Doll and Frank M. Johannes
25.3
Branch-and-Bound Placement for Building Block Layout
....................................................................................433
Hidetoshi Onodera, Yo Taniguchi and Keikichi
Tamaru
West Paper Award Candidates
xix
Session 26:
Testability Analysis
(Chair:
M. R.
Mercer; Organizers:
К. Т.
Cheng,
T.
Williams)
26.1
A Probabilistic Testability Measure for Delay Faults
............................................................................................440
Wen Ching Wu and Chung
Len
Lee
26.2
Testability of Asynchronous Timed Control Circuits with Delay Assumptions
...................................................446
Peter
A. Beerei
and Teresa H.-Y.
Meng
26.3
A Branching Process Model for Observability Analysis of Combinational Circuits
............................................452
Sarma Sastry
andAmitava Majumdar
Session
27:
Logic Optimization
(Chair: R. K. Brayton; Organizers: M.
Lightner,
A. Sangiovanni-Vincentelli)
27.1
A Resynthesis Approach for Network Optimization
.............................................................................................458
Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga and Masahiro Fujita
27.2
Logic Optimization of
MOS
Networks
..................................................................................................................464
Johnson Chan Limqueco and Saburo Muroga
21.
Ъ
Logic Minimization using Two-column Rectangle Replacement
..........................................................................470
Ѕфгеп Ѕфе
and Kevin Karplus
Session
28:
PANEL:
Are Formal Methods in Design For Real?
(Chair: G. Venzl)
Panel Members: Dominique Borrione, Randal Bryant, Jean
Christophe
Madre,
David May, Gerald Musgrave, Alberto Sangiovanni-Vincentelli
..........................................................................474
Session
29:
Module Generators
(Chair: K. Hirakawa; Organizers: G.
De Micheli,
К.
Hirakawa)
29.1
Flexible Transistor Matrix (FTM)
..........................................................................................................................475
King C. Ho and
Sarma
Sastry
29.2
An Efficient Layout Style For 2-Metal CMOS Leaf Cells And Their Automatic Generation
..............................481
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin and Yu-Chin Hsu
29.3
Exact Width and Height Minimization of CMOS Cells
........................................................................................487
Robert L. Maziasz and John P. Hayes
Session
30:
CAD for Analog Cells and ICs
(Chair: R. A.
Rutenbar;
Organizers: R.
Rutenbar,
R. Saleh)
30.1
Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time
.....................................................494
Scott D.
Huss
and Ronald S. Gyurcsik
30.2
Generation of Performance Sensitivities for Analog Cell Layout
.........................................................................500
George Gad-El-Karim and Ronald S. Gyurcsik
30.3
A Constraint Based Approach to Automatic Design of Analog Cells
...................................................................506
L.-O.
Donzelle,
P.-F.
Dubois,
В.
Hennion,
J. Parissis and P. Šerm
30.4
A
Layout
Improvement Method Based on Constraint Propagation for Analog LSI s
...........................................510
Masato
Mogakí, Naoki Kato,
Naomi Shimada and Yuriko Yamada
Session
31 :
Interfacing to High-Level Synthesis: Above and Below
(Chair: R. A. Walker; Organizers: E. Girczyc, M. McFarland, SJ)
31.1
CHOP: A Constraint-Driven System-Level Partitioner
.........................................................................................514
Kayhan
Kiiçiikçakar
and Alice C. Parker
xx
31.2
Industrial
Extensions
to University High Level Synthesis Tools: Making It Work in the Real World
.................520
Thomas E. Fuhrman
31.3
Bridging High-Level Synthesis to
RTL
Technology Libraries
..............................................................................526
Nikil D. Dutt and James R. Kipps
31.4
The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve
..................................530
Alice C. Parker,
Pravil
Gupta and Agha Hussain
Session
32:
Critical Path Analysis of Logic Gate Networks
(Chair: P. McGeer; Organizers: R. Bryant, G.
De Micheli)
32.1
An Efficient Parallel Critical Path Algorithm
........................................................................................................535
Li-Ren Liu, David
H. C. Du
and Hsi-Chuan Chen
32.2
Incremental Techniques for the Identification of Statically Sensitizable Critical Paths
........................................541
Yun-Cheng Ju and Re
sve
A. Saleh
32.3
Critical Path Selection for Performance Optimization
...........................................................................................547
Hsi-Chuan Chen, David
H. C. Du
and Li-Ren Liu
32.4
Timing Verification on a l^M-Device Full-Custom CMOS Design
....................................................................551
Jengwei Pan, Larry Biro, Joel Grodstein, Bill
Grundmann
and Yao-Tsung Yen
Session
33:
Timing Modeling of Interconnect
(Chair: M. Horowitz; Organizers: R. Bryant, G.
De Micheli)
*33.
1
RICE: Rapid Interconnect Circuit
Evaluator
.........................................................................................................555
Curtis L· Ratzlaff,
Nanda
Gopal and Lawrence T. Pillage
33.2
A New Nonlinear Driver Model for Interconnect Analysis
...................................................................................561
Vi vek
Raghavan and Ronald A. Rohrer
33.3
Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected Waves
...........567
Heinz Mattes, Wolfgang Weisenseel, Gerhard
Bischof
and Reimund
Dachauer
Session
34:
Technology CAD
(Chair: S. Nassif; Organizers: R. Saleh, A. Strojwas)
34.1
Linking TCAD to EDA
—
Benefits and Issues
.......................................................................................................573
G. Chin, W. Dietrich, Jr., D. Boning, A. Wong, A. Neureuther and R. Dutton
34.2
A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor
and Statistical Simulator
.........................................................................................................................................579
D. M. H. Walker,
C. S.
Kellen,
and
A. J. Strojwas
34.3 GOALSERVER:
A Multiobjective Design
Optimization Tool for
1С
Fabrication Process
..................................585
Lifeng Wu, Zhilian Yang, Zhiping Yu andZhijian Li
Session
35:
Synthesis of High-Performance Systems
(Chair: P. Michel; Organizers: E. Girczyc, M. McFarland, SJ)
35.1
Data-Path Synthesis Using Path Analysis
..............................................................................................................591
Reinaldo
A. Bergamaschi,
Raul Camposano and Michael Payer
*35.2 Cathedral-III: Architecture-Driven High-Level Synthesis for High Throughput DSP Applications
....................597
Stefaan Note, Werner Geurts,
Francky
Catthoor and Hugo
De Man
35.3
Data-Path Scheduling for Two-Level Pipelining
...................................................................................................603
C. Y.
Roger Chen and Michael Z.
Móricz
35.4
Relevant Issues in High-Level Connectivity Synthesis
.........................................................................................607
Barry M. Pangrle, Forrest D. Brewer, Donald
A. Lobo
and Andrew Seawright
*Best Paper Award Candidates
xxi
Session 36: PANEL:
Testability
Solutions:
Who Really Wants Them?
(Chair: A. Sangiovanni-Vincentelli)
Panel Members: Vishwani Agrawal, Tushar Gheewala, Ken
Okin,
Rob Walker, Tom Williams
........................611
Session
37:
Placement for Performance Optimization
(Chair: M. Burstein; Organizers: B. Preas, R.
Rutenbar)
37.1
Tutorial: The Role of Timing Verification in Layout Synthesis
..........................................................................612
Jacques Benkoski and
Andrzej
J.
Strojwas
37.2
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement
................................620
Ren-Song Tsay andJuergen Koehl
37.3
A Fast Physical Constraint Generator for Timing Driven Layout
.........................................................................626
Wing
K. Luk
37.4
Dynamic Prediction of Critical Paths And Nets For Constructive Timing-Driven Placement
..............................632
Suphachai Sutanthavibul and Eugene Shragowitz
37.5
An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs
........................................................636
Arvind Srinivasan
37.6
Placement for Clock Period Minimization With Multiple Wave Propagation
......................................................640
Donald A. Joy and
Maciej J. Ciesielski
Session
38:
Extending the Functionality of Discrete Simulation
(Chair: R. E. Bryant; Organizers: R. Bryant, R. Saleh)
38.1
Transition Density, A Stochastic Measure of Activity in Digital Circuits
.............................................................644
F
arid
N.
Najm
*38.2 Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits
...............................650
Yutaka Deguchi, Nagisa Ishiura and Shuzo Yajima
38.3
OEsim: A Simulator for Timing Behavior
.............................................................................................................656
Tod
Amon
and Gaetano Borriello
38.4
CLOVER: A Timing Constraints Verification System
..........................................................................................662
Dimitris Doukas and Andrea S. LaPaugh
Session
39:
Scheduling in High-Level Synthesis I
(Chair: D. Gajski; Organizers: E. Girczyc, M. McFarland, SJ)
39.1 3D
Scheduling: High-Level Synthesis with Floorplanning
...................................................................................668
Jen-Pin Weng and Alice C. Parker
39.2
Bottom Up Synthesis Based on Fuzzy Schedules
..................................................................................................674
Tai
A. Ly and Jack T. Mowchenko
39.3
Fast and Near Optimal Scheduling in Automatic Data Path Synthesis
..................................................................680
In-Cheol Park and Chong-Min Kyung
39.4
Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics
.......................................................686
Rajiv Jain, Ashutosh Mujumdar, Alok Sharma and Hueymin Wang
39.5
Sizing Synchronization Queues: A Case Study in Higher Level Synthesis
...........................................................690
Tod
Amon
and Gaetano Borriello
Session
40:
Frameworks
(Chair: J. Mermet; Organizers: D. Hill, E. Yoffa)
*40.1 The
MCC
CAD Framework Methodology Management System
..........................................................................694
Wayne Allen, Douglas
Rosenthal
and Kenneth Fiduk
40.2
A Configuration Management System in a Data Management Framework
..........................................................699
Steve Banks, Catherine Bunting,
Russ
Edwards, Laura Fleming and Peter
Hacken
*Best Paper Award Candidates
XXII
40.3
Design Version Management
in the GARDEN Framework
..................................................................................704
Flávio
R.
Wagner and
Arnaldo
H. Vie
gas de Lima
40.4
Design
Flow
Management
in the NELSIS CAD Framework
................................................................................711
K. O. ten Bosch, P. Bingley and P. van
der
Wolf
Session
41:
Geometric Algorithms
(Chair: D. Boyer; Organizers: D. Hill, K. Hirakawa)
41.1
REX
—
A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis
...........................................717
Jerry P. Hwang
41.2
A New Approach to Hierarchical Adaptation Using Sequence-Control Based on Cell Interactions
....................723
Matthias
С
Utesch
41.3
A Two-Dimensional Topological Compactor With Octagonal Geometry
............................................................727
Paul
de Dood,
John Wawrzynek,
Erwin
Liu and Roberto Suaya
41.4
VLSI Layout Compaction Using Radix Priority Search Trees
..............................................................................732
Andrew J. Harrison
41.5
On Minimal Closure Constraint Generation for Symbolic Cell Assembly
............................................................736
Debaprosad Dutt and
Chi-Yuan Lo
Session
42:
Transmission Line and Interconnect Simulation
(Chair: K.
Kundért;
Organizers: R. Saleh, A. Strojwas)
*42.1 Efficient Transient Simulation of Lossy Interconnect
...........................................................................................740
Jaijeet S. Roychowdhury and Donald O. Pederson
42.2
A Transmission Line Simulator for GaAs Integrated Circuits
...............................................................................746
J. S. Barkatullah and S. Chowdhury
42.3
Modeling and Simulation of High-Frequency Integrated Circuits Based on Scattering Parameters
.....................752
A. T. Yang,
C. H.
Chan, J. T. Yao, R. R. Daniels and J. P. Harrang
Session
43:
Scheduling in High-Level Synthesis II
(Chair: G.
De Micheli;
Organizers:
G. De
Micheli,
M.
Lightner)
43.1
Minimizing The Number of Delay Buffers In The Synchronization Of Pipelined Systems
.................................758
X.
Ни,
R. G.
HarberandS.
С.
Bass
43.2
Scheduling for Functional Pipelining and Loop Winding
.....................................................................................764
Cheng-Tsung Hwang, Yu-Chin Hsu and Youn-Long Lin
43.3
Incremental Tree Height Reduction For High Level Synthesis
.............................................................................770
Alexandru
Nicolau
and
Roni Potasman
43.4
Redundant Operator Creation: A Scheduling Optimization Technique
.................................................................775
Donald
A. Lobo
and Barry M. Pangrle
Session
44:
PANEL:
Will the Field-Programmable Gate Array
Repiace
the Mask-Programmable Gate Array?
(Chair: J. Rose)
Panel Members:
Ewald
Detjens, Jonathan Greene, Wayne Spence, Steve Trimberger
Ed Vopni, Rob Walker
...........................................................................................................................................779
*Best Paper Award Candidates
|
| any_adam_object | 1 |
| author_corporate | Design Automation Conference (Association for Computing Machinery) San Francisco, Calif |
| author_corporate_role | aut |
| author_facet | Design Automation Conference (Association for Computing Machinery) San Francisco, Calif |
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| bvnumber | BV005924089 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)630424576 (DE-599)BVBBV005924089 |
| discipline | Elektrotechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1991 San Francisco Calif. gnd-content |
| genre_facet | Konferenzschrift 1991 San Francisco Calif. |
| id | DE-604.BV005924089 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:36:57Z |
| institution | BVB |
| institution_GND | (DE-588)5065346-5 |
| isbn | 0897913957 0818691492 0818661496 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-003709731 |
| oclc_num | 630424576 |
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| owner_facet | DE-91 DE-BY-TUM DE-91G DE-BY-TUM DE-20 DE-83 |
| physical | XXIII, 783 S. graph. Darst. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| publisher | Assoc. for Computing Machinery |
| record_format | marc |
| spelling | Design Automation Conference (Association for Computing Machinery) 28 1991 San Francisco, Calif. Verfasser (DE-588)5065346-5 aut Proceedings 1991 June 17 - 21, 1991 San Francisco, California, Moscone Center 28th ACM/IEEE Design Automation Conference ; [general chair A. Richard Newton] New York, NY Assoc. for Computing Machinery 1991 XXIII, 783 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Entwurf (DE-588)4121208-3 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1991 San Francisco Calif. gnd-content Integrierte Schaltung (DE-588)4027242-4 s Entwurf (DE-588)4121208-3 s DE-604 Newton, A. R. Sonstige oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=003709731&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings 1991 June 17 - 21, 1991 San Francisco, California, Moscone Center Entwurf (DE-588)4121208-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4027242-4 (DE-588)1071861417 |
| title | Proceedings 1991 June 17 - 21, 1991 San Francisco, California, Moscone Center |
| title_auth | Proceedings 1991 June 17 - 21, 1991 San Francisco, California, Moscone Center |
| title_exact_search | Proceedings 1991 June 17 - 21, 1991 San Francisco, California, Moscone Center |
| title_full | Proceedings 1991 June 17 - 21, 1991 San Francisco, California, Moscone Center 28th ACM/IEEE Design Automation Conference ; [general chair A. Richard Newton] |
| title_fullStr | Proceedings 1991 June 17 - 21, 1991 San Francisco, California, Moscone Center 28th ACM/IEEE Design Automation Conference ; [general chair A. Richard Newton] |
| title_full_unstemmed | Proceedings 1991 June 17 - 21, 1991 San Francisco, California, Moscone Center 28th ACM/IEEE Design Automation Conference ; [general chair A. Richard Newton] |
| title_short | Proceedings 1991 |
| title_sort | proceedings 1991 june 17 21 1991 san francisco california moscone center |
| title_sub | June 17 - 21, 1991 San Francisco, California, Moscone Center |
| topic | Entwurf (DE-588)4121208-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Entwurf Integrierte Schaltung Konferenzschrift 1991 San Francisco Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=003709731&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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