RISC architectures:
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Buch |
Sprache: | English French |
Veröffentlicht: |
London u.a.
Chapman & Hall
1992
|
Ausgabe: | 1. ed. |
Schlagworte: | |
Beschreibung: | Literaturverz. S. 238 - 251 |
Beschreibung: | IX, 261 S. |
ISBN: | 0412453401 0442316054 |
Internformat
MARC
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Datensatz im Suchindex
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any_adam_object | |
author | Heudin, J. C. Panetto, C. |
author_facet | Heudin, J. C. Panetto, C. |
author_role | aut aut |
author_sort | Heudin, J. C. |
author_variant | j c h jc jch c p cp |
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bvnumber | BV005617946 |
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dewey-tens | 000 - Computer science, information, general works |
discipline | Informatik |
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id | DE-604.BV005617946 |
illustrated | Not Illustrated |
indexdate | 2024-07-09T16:32:19Z |
institution | BVB |
isbn | 0412453401 0442316054 |
language | English French |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-003515891 |
oclc_num | 26543167 |
open_access_boolean | |
owner | DE-91 DE-BY-TUM DE-739 DE-Aug4 DE-706 DE-634 |
owner_facet | DE-91 DE-BY-TUM DE-739 DE-Aug4 DE-706 DE-634 |
physical | IX, 261 S. |
publishDate | 1992 |
publishDateSearch | 1992 |
publishDateSort | 1992 |
publisher | Chapman & Hall |
record_format | marc |
spelling | Heudin, J. C. Verfasser aut Les architectures RISC RISC architectures J. C. Heudin and C. Panetto 1. ed. London u.a. Chapman & Hall 1992 IX, 261 S. txt rdacontent n rdamedia nc rdacarrier Literaturverz. S. 238 - 251 Computer architecture RISC microprocessors Reduced instruction set computers RISC (DE-588)4191875-7 gnd rswk-swf RISC (DE-588)4191875-7 s DE-604 Panetto, C. Verfasser aut |
spellingShingle | Heudin, J. C. Panetto, C. RISC architectures Computer architecture RISC microprocessors Reduced instruction set computers RISC (DE-588)4191875-7 gnd |
subject_GND | (DE-588)4191875-7 |
title | RISC architectures |
title_alt | Les architectures RISC |
title_auth | RISC architectures |
title_exact_search | RISC architectures |
title_full | RISC architectures J. C. Heudin and C. Panetto |
title_fullStr | RISC architectures J. C. Heudin and C. Panetto |
title_full_unstemmed | RISC architectures J. C. Heudin and C. Panetto |
title_short | RISC architectures |
title_sort | risc architectures |
topic | Computer architecture RISC microprocessors Reduced instruction set computers RISC (DE-588)4191875-7 gnd |
topic_facet | Computer architecture RISC microprocessors Reduced instruction set computers RISC |
work_keys_str_mv | AT heudinjc lesarchitecturesrisc AT panettoc lesarchitecturesrisc AT heudinjc riscarchitectures AT panettoc riscarchitectures |