Chip-level modeling with VHDL:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Englewood Cliffs, NJ
Prentice Hall
1989
|
| Schlagworte: | |
| Beschreibung: | X, 148 S. graph. Darst. |
| ISBN: | 0131331906 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV005554396 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 920915s1989 d||| |||| 00||| eng d | ||
| 020 | |a 0131331906 |9 0-13-133190-6 | ||
| 035 | |a (OCoLC)263668284 | ||
| 035 | |a (DE-599)BVBBV005554396 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-92 |a DE-739 |a DE-29T |a DE-859 |a DE-898 | ||
| 084 | |a ST 190 |0 (DE-625)143607: |2 rvk | ||
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 084 | |a ZN 4952 |0 (DE-625)157425: |2 rvk | ||
| 084 | |a ZN 5400 |0 (DE-625)157454: |2 rvk | ||
| 100 | 1 | |a Armstrong, James R. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Chip-level modeling with VHDL |
| 264 | 1 | |a Englewood Cliffs, NJ |b Prentice Hall |c 1989 | |
| 300 | |a X, 148 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Computersimulation |0 (DE-588)4148259-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | 2 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Computersimulation |0 (DE-588)4148259-1 |D s |
| 689 | 1 | |8 1\p |5 DE-604 | |
| 689 | 2 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 2 | |8 2\p |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-003482997 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804119775113117696 |
|---|---|
| any_adam_object | |
| author | Armstrong, James R. |
| author_facet | Armstrong, James R. |
| author_role | aut |
| author_sort | Armstrong, James R. |
| author_variant | j r a jr jra |
| building | Verbundindex |
| bvnumber | BV005554396 |
| classification_rvk | ST 190 ST 250 ZN 4952 ZN 5400 |
| ctrlnum | (OCoLC)263668284 (DE-599)BVBBV005554396 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01741nam a2200481 c 4500</leader><controlfield tag="001">BV005554396</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">920915s1989 d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0131331906</subfield><subfield code="9">0-13-133190-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)263668284</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV005554396</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-92</subfield><subfield code="a">DE-739</subfield><subfield code="a">DE-29T</subfield><subfield code="a">DE-859</subfield><subfield code="a">DE-898</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4952</subfield><subfield code="0">(DE-625)157425:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5400</subfield><subfield code="0">(DE-625)157454:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Armstrong, James R.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Chip-level modeling with VHDL</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Englewood Cliffs, NJ</subfield><subfield code="b">Prentice Hall</subfield><subfield code="c">1989</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">X, 148 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Computersimulation</subfield><subfield code="0">(DE-588)4148259-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Computersimulation</subfield><subfield code="0">(DE-588)4148259-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-003482997</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| id | DE-604.BV005554396 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:31:33Z |
| institution | BVB |
| isbn | 0131331906 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-003482997 |
| oclc_num | 263668284 |
| open_access_boolean | |
| owner | DE-92 DE-739 DE-29T DE-859 DE-898 DE-BY-UBR |
| owner_facet | DE-92 DE-739 DE-29T DE-859 DE-898 DE-BY-UBR |
| physical | X, 148 S. graph. Darst. |
| publishDate | 1989 |
| publishDateSearch | 1989 |
| publishDateSort | 1989 |
| publisher | Prentice Hall |
| record_format | marc |
| spelling | Armstrong, James R. Verfasser aut Chip-level modeling with VHDL Englewood Cliffs, NJ Prentice Hall 1989 X, 148 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier VLSI (DE-588)4117388-0 gnd rswk-swf Computersimulation (DE-588)4148259-1 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf VLSI (DE-588)4117388-0 s Schaltungsentwurf (DE-588)4179389-4 s VHDL (DE-588)4254792-1 s DE-604 Computersimulation (DE-588)4148259-1 s 1\p DE-604 Integrierte Schaltung (DE-588)4027242-4 s 2\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Armstrong, James R. Chip-level modeling with VHDL VLSI (DE-588)4117388-0 gnd Computersimulation (DE-588)4148259-1 gnd VHDL (DE-588)4254792-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4148259-1 (DE-588)4254792-1 (DE-588)4179389-4 (DE-588)4027242-4 |
| title | Chip-level modeling with VHDL |
| title_auth | Chip-level modeling with VHDL |
| title_exact_search | Chip-level modeling with VHDL |
| title_full | Chip-level modeling with VHDL |
| title_fullStr | Chip-level modeling with VHDL |
| title_full_unstemmed | Chip-level modeling with VHDL |
| title_short | Chip-level modeling with VHDL |
| title_sort | chip level modeling with vhdl |
| topic | VLSI (DE-588)4117388-0 gnd Computersimulation (DE-588)4148259-1 gnd VHDL (DE-588)4254792-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | VLSI Computersimulation VHDL Schaltungsentwurf Integrierte Schaltung |
| work_keys_str_mv | AT armstrongjamesr chiplevelmodelingwithvhdl |