Layout minimization of CMOS cells:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
1992
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
160 : VLSI, computer architecture and digital signal processing |
| Schlagworte: | |
| Beschreibung: | Literaturverz. S. 157 - 165 |
| Beschreibung: | XII, 169 S. graph. Darst. |
| ISBN: | 0792391829 |
Internformat
MARC
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| 003 | DE-604 | ||
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| 035 | |a (DE-599)BVBBV005451305 | ||
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| 084 | |a ZN 4960 |0 (DE-625)157426: |2 rvk | ||
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| 100 | 1 | |a Maziasz, Robert L. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Layout minimization of CMOS cells |c by Robert L. Maziasz and John P. Hayes |
| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 1992 | |
| 300 | |a XII, 169 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 160 : VLSI, computer architecture and digital signal processing | |
| 500 | |a Literaturverz. S. 157 - 165 | ||
| 650 | 7 | |a Conception assistée par ordinateur |2 ram | |
| 650 | 7 | |a MOS complémentaires - Conception et construction |2 ram | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary |x Computer-aided design | |
| 650 | 0 | 7 | |a CMOS |0 (DE-588)4010319-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CMOS-Speicher |0 (DE-588)4278777-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Layout |g Mikroelektronik |0 (DE-588)4264372-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Minimierung |0 (DE-588)4251074-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Layout |g Mikroelektronik |0 (DE-588)4264372-7 |D s |
| 689 | 0 | 1 | |a Minimierung |0 (DE-588)4251074-0 |D s |
| 689 | 0 | 2 | |a CMOS |0 (DE-588)4010319-5 |D s |
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| 689 | 1 | 0 | |a CMOS-Speicher |0 (DE-588)4278777-4 |D s |
| 689 | 1 | 1 | |a Layout |g Mikroelektronik |0 (DE-588)4264372-7 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a CMOS-Speicher |0 (DE-588)4278777-4 |D s |
| 689 | 2 | 1 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 2 | |5 DE-604 | |
| 700 | 1 | |a Hayes, John P. |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 160 : VLSI, computer architecture and digital signal processing |w (DE-604)BV023545171 |9 160 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-003409800 | ||
Datensatz im Suchindex
| _version_ | 1804119660675727360 |
|---|---|
| any_adam_object | |
| author | Maziasz, Robert L. Hayes, John P. |
| author_facet | Maziasz, Robert L. Hayes, John P. |
| author_role | aut aut |
| author_sort | Maziasz, Robert L. |
| author_variant | r l m rl rlm j p h jp jph |
| building | Verbundindex |
| bvnumber | BV005451305 |
| callnumber-first | T - Technology |
| callnumber-label | TK7871 |
| callnumber-raw | TK7871.99.M44 |
| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)24429749 (DE-599)BVBBV005451305 |
| dewey-full | 621.381/52 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381/52 |
| dewey-search | 621.381/52 |
| dewey-sort | 3621.381 252 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV005451305 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:29:44Z |
| institution | BVB |
| isbn | 0792391829 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-003409800 |
| oclc_num | 24429749 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-29T |
| owner_facet | DE-91 DE-BY-TUM DE-29T |
| physical | XII, 169 S. graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | Kluwer |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Maziasz, Robert L. Verfasser aut Layout minimization of CMOS cells by Robert L. Maziasz and John P. Hayes Boston [u.a.] Kluwer 1992 XII, 169 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 160 : VLSI, computer architecture and digital signal processing Literaturverz. S. 157 - 165 Conception assistée par ordinateur ram MOS complémentaires - Conception et construction ram Metal oxide semiconductors, Complementary Computer-aided design CMOS (DE-588)4010319-5 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf CMOS-Speicher (DE-588)4278777-4 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Minimierung (DE-588)4251074-0 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 s Minimierung (DE-588)4251074-0 s CMOS (DE-588)4010319-5 s DE-604 CMOS-Speicher (DE-588)4278777-4 s Schaltungsentwurf (DE-588)4179389-4 s Hayes, John P. Verfasser aut The Kluwer international series in engineering and computer science 160 : VLSI, computer architecture and digital signal processing (DE-604)BV023545171 160 |
| spellingShingle | Maziasz, Robert L. Hayes, John P. Layout minimization of CMOS cells The Kluwer international series in engineering and computer science Conception assistée par ordinateur ram MOS complémentaires - Conception et construction ram Metal oxide semiconductors, Complementary Computer-aided design CMOS (DE-588)4010319-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd CMOS-Speicher (DE-588)4278777-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Minimierung (DE-588)4251074-0 gnd |
| subject_GND | (DE-588)4010319-5 (DE-588)4179389-4 (DE-588)4278777-4 (DE-588)4264372-7 (DE-588)4251074-0 |
| title | Layout minimization of CMOS cells |
| title_auth | Layout minimization of CMOS cells |
| title_exact_search | Layout minimization of CMOS cells |
| title_full | Layout minimization of CMOS cells by Robert L. Maziasz and John P. Hayes |
| title_fullStr | Layout minimization of CMOS cells by Robert L. Maziasz and John P. Hayes |
| title_full_unstemmed | Layout minimization of CMOS cells by Robert L. Maziasz and John P. Hayes |
| title_short | Layout minimization of CMOS cells |
| title_sort | layout minimization of cmos cells |
| topic | Conception assistée par ordinateur ram MOS complémentaires - Conception et construction ram Metal oxide semiconductors, Complementary Computer-aided design CMOS (DE-588)4010319-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd CMOS-Speicher (DE-588)4278777-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Minimierung (DE-588)4251074-0 gnd |
| topic_facet | Conception assistée par ordinateur MOS complémentaires - Conception et construction Metal oxide semiconductors, Complementary Computer-aided design CMOS Schaltungsentwurf CMOS-Speicher Layout Mikroelektronik Minimierung |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT maziaszrobertl layoutminimizationofcmoscells AT hayesjohnp layoutminimizationofcmoscells |