Sequential logic synthesis:
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | Undetermined |
| Published: |
Boston u.a.
Kluwer Acad.
1992
|
| Series: | The Kluwer international series in engineering and computer science
162 |
| Subjects: | |
| Item Description: | Literaturverz. S. 209 - 219 |
| Physical Description: | XV, 225 S. graph. Darst. |
| ISBN: | 079239187X |
Staff View
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV005125737 | ||
| 003 | DE-604 | ||
| 005 | 19920615 | ||
| 007 | t | ||
| 008 | 920604s1992 d||| |||| 00||| undod | ||
| 020 | |a 079239187X |9 0-7923-9187-X | ||
| 035 | |a (OCoLC)246512515 | ||
| 035 | |a (DE-599)BVBBV005125737 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | |a und | ||
| 049 | |a DE-91 |a DE-12 |a DE-739 |a DE-29T | ||
| 084 | |a ST 190 |0 (DE-625)143607: |2 rvk | ||
| 084 | |a DAT 550f |2 stub | ||
| 084 | |a ELT 459f |2 stub | ||
| 100 | 1 | |a Ashar, Pranav |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Sequential logic synthesis |c by Pranav Ashar ; Srinivas Devadas ; A. Richard Newton |
| 264 | 1 | |a Boston u.a. |b Kluwer Acad. |c 1992 | |
| 300 | |a XV, 225 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 162 | |
| 500 | |a Literaturverz. S. 209 - 219 | ||
| 650 | 0 | 7 | |a Schaltwerk |0 (DE-588)4052057-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Automatentheorie |0 (DE-588)4003953-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Datenverarbeitung |0 (DE-588)4011152-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Automatentheorie |0 (DE-588)4003953-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Schaltwerk |0 (DE-588)4052057-2 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 2 | 1 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 2 | |5 DE-604 | |
| 689 | 3 | 0 | |a Datenverarbeitung |0 (DE-588)4011152-0 |D s |
| 689 | 3 | 1 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
| 689 | 3 | 2 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 3 | |5 DE-604 | |
| 700 | 1 | |a Devadas, Srinivas |d 1963- |e Verfasser |0 (DE-588)121371107 |4 aut | |
| 700 | 1 | |a Newton, Arthur R. |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 162 |w (DE-604)BV023545171 |9 162 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-003152586 | ||
Record in the Search Index
| _version_ | 1804119257735233536 |
|---|---|
| any_adam_object | |
| author | Ashar, Pranav Devadas, Srinivas 1963- Newton, Arthur R. |
| author_GND | (DE-588)121371107 |
| author_facet | Ashar, Pranav Devadas, Srinivas 1963- Newton, Arthur R. |
| author_role | aut aut aut |
| author_sort | Ashar, Pranav |
| author_variant | p a pa s d sd a r n ar arn |
| building | Verbundindex |
| bvnumber | BV005125737 |
| classification_rvk | ST 190 |
| classification_tum | DAT 550f ELT 459f |
| ctrlnum | (OCoLC)246512515 (DE-599)BVBBV005125737 |
| discipline | Informatik Elektrotechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02049nam a2200553 cb4500</leader><controlfield tag="001">BV005125737</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19920615 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">920604s1992 d||| |||| 00||| undod</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">079239187X</subfield><subfield code="9">0-7923-9187-X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)246512515</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV005125737</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-12</subfield><subfield code="a">DE-739</subfield><subfield code="a">DE-29T</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 550f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 459f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Ashar, Pranav</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Sequential logic synthesis</subfield><subfield code="c">by Pranav Ashar ; Srinivas Devadas ; A. Richard Newton</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston u.a.</subfield><subfield code="b">Kluwer Acad.</subfield><subfield code="c">1992</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XV, 225 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">The Kluwer international series in engineering and computer science</subfield><subfield code="v">162</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Literaturverz. S. 209 - 219</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltwerk</subfield><subfield code="0">(DE-588)4052057-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Automatentheorie</subfield><subfield code="0">(DE-588)4003953-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Datenverarbeitung</subfield><subfield code="0">(DE-588)4011152-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Automatentheorie</subfield><subfield code="0">(DE-588)4003953-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Schaltwerk</subfield><subfield code="0">(DE-588)4052057-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Datenverarbeitung</subfield><subfield code="0">(DE-588)4011152-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2="1"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2="2"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Devadas, Srinivas</subfield><subfield code="d">1963-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)121371107</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Newton, Arthur R.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">The Kluwer international series in engineering and computer science</subfield><subfield code="v">162</subfield><subfield code="w">(DE-604)BV023545171</subfield><subfield code="9">162</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-003152586</subfield></datafield></record></collection> |
| id | DE-604.BV005125737 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:23:19Z |
| institution | BVB |
| isbn | 079239187X |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-003152586 |
| oclc_num | 246512515 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-12 DE-739 DE-29T |
| owner_facet | DE-91 DE-BY-TUM DE-12 DE-739 DE-29T |
| physical | XV, 225 S. graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | Kluwer Acad. |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Ashar, Pranav Verfasser aut Sequential logic synthesis by Pranav Ashar ; Srinivas Devadas ; A. Richard Newton Boston u.a. Kluwer Acad. 1992 XV, 225 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 162 Literaturverz. S. 209 - 219 Schaltwerk (DE-588)4052057-2 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Automatentheorie (DE-588)4003953-5 gnd rswk-swf Datenverarbeitung (DE-588)4011152-0 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Automatentheorie (DE-588)4003953-5 s DE-604 Schaltwerk (DE-588)4052057-2 s VLSI (DE-588)4117388-0 s CAD (DE-588)4069794-0 s Datenverarbeitung (DE-588)4011152-0 s Logischer Entwurf (DE-588)4168051-0 s Devadas, Srinivas 1963- Verfasser (DE-588)121371107 aut Newton, Arthur R. Verfasser aut The Kluwer international series in engineering and computer science 162 (DE-604)BV023545171 162 |
| spellingShingle | Ashar, Pranav Devadas, Srinivas 1963- Newton, Arthur R. Sequential logic synthesis The Kluwer international series in engineering and computer science Schaltwerk (DE-588)4052057-2 gnd CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd Automatentheorie (DE-588)4003953-5 gnd Datenverarbeitung (DE-588)4011152-0 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| subject_GND | (DE-588)4052057-2 (DE-588)4069794-0 (DE-588)4117388-0 (DE-588)4003953-5 (DE-588)4011152-0 (DE-588)4168051-0 |
| title | Sequential logic synthesis |
| title_auth | Sequential logic synthesis |
| title_exact_search | Sequential logic synthesis |
| title_full | Sequential logic synthesis by Pranav Ashar ; Srinivas Devadas ; A. Richard Newton |
| title_fullStr | Sequential logic synthesis by Pranav Ashar ; Srinivas Devadas ; A. Richard Newton |
| title_full_unstemmed | Sequential logic synthesis by Pranav Ashar ; Srinivas Devadas ; A. Richard Newton |
| title_short | Sequential logic synthesis |
| title_sort | sequential logic synthesis |
| topic | Schaltwerk (DE-588)4052057-2 gnd CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd Automatentheorie (DE-588)4003953-5 gnd Datenverarbeitung (DE-588)4011152-0 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| topic_facet | Schaltwerk CAD VLSI Automatentheorie Datenverarbeitung Logischer Entwurf |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT asharpranav sequentiallogicsynthesis AT devadassrinivas sequentiallogicsynthesis AT newtonarthurr sequentiallogicsynthesis |