Sequential logic testing and verification:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer Acad. Publ.
1992
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
163 |
| Schlagworte: | |
| Beschreibung: | Literaturverz. S. 199 - 211 |
| Beschreibung: | XV, 214 S. graph. Darst. |
| ISBN: | 0792391888 |
Internformat
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| 100 | 1 | |a Ghosh, Abhijit |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Sequential logic testing and verification |c by Abhijit Ghosh ; Srinivas Devadas ; A. Richard Newton |
| 264 | 1 | |a Boston [u.a.] |b Kluwer Acad. Publ. |c 1992 | |
| 300 | |a XV, 214 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 163 | |
| 500 | |a Literaturverz. S. 199 - 211 | ||
| 650 | 7 | |a Circuits intégrés à très grande échelle - Essais |2 ram | |
| 650 | 7 | |a Circuits intégrés à très grande échelle - Fiabilité |2 ram | |
| 650 | 4 | |a Circuits logiques - Essais | |
| 650 | 7 | |a Circuits logiques - Essais |2 ram | |
| 650 | 4 | |a Conception assistée par ordinateur | |
| 650 | 4 | |a Fiabilité circuit séquentiel | |
| 650 | 4 | |a Logique séquentielle | |
| 650 | 4 | |a Structure logique | |
| 650 | 4 | |a Test VLSI | |
| 650 | 4 | |a Test circuit logique | |
| 650 | 4 | |a Computer-aided design | |
| 650 | 4 | |a Logic circuits |x Testing | |
| 650 | 4 | |a Logic design | |
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| 650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
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| 689 | 2 | |5 DE-604 | |
| 700 | 1 | |a Devadas, Srinivas |d 1963- |e Verfasser |0 (DE-588)121371107 |4 aut | |
| 700 | 1 | |a Newton, Arthur R. |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 163 |w (DE-604)BV023545171 |9 163 | |
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Datensatz im Suchindex
| _version_ | 1804119219835502592 |
|---|---|
| any_adam_object | |
| author | Ghosh, Abhijit Devadas, Srinivas 1963- Newton, Arthur R. |
| author_GND | (DE-588)121371107 |
| author_facet | Ghosh, Abhijit Devadas, Srinivas 1963- Newton, Arthur R. |
| author_role | aut aut aut |
| author_sort | Ghosh, Abhijit |
| author_variant | a g ag s d sd a r n ar arn |
| building | Verbundindex |
| bvnumber | BV005099195 |
| callnumber-first | T - Technology |
| callnumber-label | TK7868 |
| callnumber-raw | TK7868.L6 |
| callnumber-search | TK7868.L6 |
| callnumber-sort | TK 47868 L6 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 190 |
| classification_tum | ELT 468f |
| ctrlnum | (OCoLC)24544043 (DE-599)BVBBV005099195 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV005099195 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:22:43Z |
| institution | BVB |
| isbn | 0792391888 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-003128948 |
| oclc_num | 24544043 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-12 DE-739 DE-29T |
| owner_facet | DE-91 DE-BY-TUM DE-12 DE-739 DE-29T |
| physical | XV, 214 S. graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | Kluwer Acad. Publ. |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Ghosh, Abhijit Verfasser aut Sequential logic testing and verification by Abhijit Ghosh ; Srinivas Devadas ; A. Richard Newton Boston [u.a.] Kluwer Acad. Publ. 1992 XV, 214 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 163 Literaturverz. S. 199 - 211 Circuits intégrés à très grande échelle - Essais ram Circuits intégrés à très grande échelle - Fiabilité ram Circuits logiques - Essais Circuits logiques - Essais ram Conception assistée par ordinateur Fiabilité circuit séquentiel Logique séquentielle Structure logique Test VLSI Test circuit logique Computer-aided design Logic circuits Testing Logic design Schaltwerk (DE-588)4052057-2 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Testen (DE-588)4367264-4 gnd rswk-swf Schaltwerk (DE-588)4052057-2 s Testen (DE-588)4367264-4 s DE-604 Logische Schaltung (DE-588)4131023-8 s Entwurf (DE-588)4121208-3 s Test (DE-588)4059549-3 s Logischer Entwurf (DE-588)4168051-0 s Devadas, Srinivas 1963- Verfasser (DE-588)121371107 aut Newton, Arthur R. Verfasser aut The Kluwer international series in engineering and computer science 163 (DE-604)BV023545171 163 |
| spellingShingle | Ghosh, Abhijit Devadas, Srinivas 1963- Newton, Arthur R. Sequential logic testing and verification The Kluwer international series in engineering and computer science Circuits intégrés à très grande échelle - Essais ram Circuits intégrés à très grande échelle - Fiabilité ram Circuits logiques - Essais Circuits logiques - Essais ram Conception assistée par ordinateur Fiabilité circuit séquentiel Logique séquentielle Structure logique Test VLSI Test circuit logique Computer-aided design Logic circuits Testing Logic design Schaltwerk (DE-588)4052057-2 gnd Logische Schaltung (DE-588)4131023-8 gnd Logischer Entwurf (DE-588)4168051-0 gnd Test (DE-588)4059549-3 gnd Entwurf (DE-588)4121208-3 gnd Testen (DE-588)4367264-4 gnd |
| subject_GND | (DE-588)4052057-2 (DE-588)4131023-8 (DE-588)4168051-0 (DE-588)4059549-3 (DE-588)4121208-3 (DE-588)4367264-4 |
| title | Sequential logic testing and verification |
| title_auth | Sequential logic testing and verification |
| title_exact_search | Sequential logic testing and verification |
| title_full | Sequential logic testing and verification by Abhijit Ghosh ; Srinivas Devadas ; A. Richard Newton |
| title_fullStr | Sequential logic testing and verification by Abhijit Ghosh ; Srinivas Devadas ; A. Richard Newton |
| title_full_unstemmed | Sequential logic testing and verification by Abhijit Ghosh ; Srinivas Devadas ; A. Richard Newton |
| title_short | Sequential logic testing and verification |
| title_sort | sequential logic testing and verification |
| topic | Circuits intégrés à très grande échelle - Essais ram Circuits intégrés à très grande échelle - Fiabilité ram Circuits logiques - Essais Circuits logiques - Essais ram Conception assistée par ordinateur Fiabilité circuit séquentiel Logique séquentielle Structure logique Test VLSI Test circuit logique Computer-aided design Logic circuits Testing Logic design Schaltwerk (DE-588)4052057-2 gnd Logische Schaltung (DE-588)4131023-8 gnd Logischer Entwurf (DE-588)4168051-0 gnd Test (DE-588)4059549-3 gnd Entwurf (DE-588)4121208-3 gnd Testen (DE-588)4367264-4 gnd |
| topic_facet | Circuits intégrés à très grande échelle - Essais Circuits intégrés à très grande échelle - Fiabilité Circuits logiques - Essais Conception assistée par ordinateur Fiabilité circuit séquentiel Logique séquentielle Structure logique Test VLSI Test circuit logique Computer-aided design Logic circuits Testing Logic design Schaltwerk Logische Schaltung Logischer Entwurf Test Entwurf Testen |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT ghoshabhijit sequentiallogictestingandverification AT devadassrinivas sequentiallogictestingandverification AT newtonarthurr sequentiallogictestingandverification |