ESSDERC 90: 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990
Gespeichert in:
| Körperschaft: | |
|---|---|
| Weitere Verfasser: | |
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Bristol [u.a.]
Hilger
1990
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXIX, 637 S. Ill., graph. Darst. |
| ISBN: | 0750300655 |
Internformat
MARC
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| 245 | 1 | 0 | |a ESSDERC 90 |b 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 |c organized by the Institute of Physics. ed. by W. Eccleston ... |
| 264 | 1 | |a Bristol [u.a.] |b Hilger |c 1990 | |
| 300 | |a XXIX, 637 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-002838091 | ||
Datensatz im Suchindex
| _version_ | 1804118738351423488 |
|---|---|
| adam_text | Contents
MONDAY MORNING SESSION
Session IIP room Bl: Invited Papers
08:45
Opening Address
09:00
1IP1
Progress in high-frequency heterojunction field effect transistors§
619
L F
Eastman
Cornell University, USA
10:00
1IP2
Novel applications of porous silicons
613
J
Keen
Royal Signals and Radar Establishment, Great Malvern, UK
10:45
COFFEE
Session
1
A room Bl: Silicon on Insulator I
11:15
1A1
Characterisation of interface electron state distributions at directly
bonded silicon/silicon interfaces
1
S
Bengtsson
and
O Engström
Chalmers University of Technology,
Göteborg,
Sweden
11:30
1A2
Assessment of
SIMOX
material by optical waveguide losses
5
N
M
Kassimt,
H P
Hot,
T M
Bensont and
D E
Daviesţ
f
University of Nottingham, UK, JEOARD, London, UK
11:45
1A3
High density
3D
CMOS circuits with
ELO
soi
technology
9
G
Roos,
В
Hoefflinger
and R Zingg
Institute for Microelectronics, Stuttgart,
W
Germany
12:00
1A4
Rounded edge mesa for
submicron
SOI CMOS process
13
О
Le Néel, M
D
BruniJ,
·*
GalvierJ and M
Haondţ
+
MATRA-MHS, Nantes, France, JCNET, Meylan, France
§
Paper
submitted
late
vi
Contents
Session
IB room C4: Heterojunction Transistor Structures
11:15
IBI
High quality pseudomorphic InGaAs/GaAs HFET structures grown by
MBE
17
С
Wölk,
F
Berlec and
H Brugger
Daimler
Benz AG, Ulm,
W Germany
11:30
1B2
Modelling the parasitic effects in GaAs/GaAlAs heterojunction bipolar
transistors
21
J
Dangla,
M
Filoche, A Koncyzkowska and
E
Caquot
Centre National
d Etudes des Télécommunications, Laboratoire de
Bagneux, France
11:45
1B3
Design, simulation
and measurement of high efficiency microwave
power heterojunction bipolar transistors
25
J
G
Metcalfe,
R
W
Allen,
A J
Holden,
A P Long and
R
Nicklin
Plessey Research Caswell Ltd, Towcester, UK
12:00
1B4
Microwave HBT fabrication by using a self-aligned technology with a
perpendicular side-wall Mesa
29
X Chen and
Y Wu
Nanjing Electronic Devices Institute, Nanjing, China
12:15
1B5
High-frequency properties and application of invertible GalnAsP/InP
double-heterostructure bipolar transistors
33
A Paraskevopoulos,
H G
Bach,
H
Schroeter-Janßen,
G Mekonnen,
H
J Hensel
and
N
Grote
Heinrich-Hertz-Institut für Nachrichtentechnik, Berlin GmbH,
W
Germany
Session 1С
Room
ВІЗ:
Advanced Silicon Device
Concepts
11:15
ICI
Frequency performances of
MOS
compatible silicon permeable base
transistors and comparison with simulation results
37
M
Mouist,
P
Letourneau* and
G Vincent§
f
Institut d Electronique Fondamentale, Orsay, France. JCNET,
Meylan. France,
§
Université Joseph
Fourier,
Grenoble. France
11:30
1C2
P-Channel etched-groove Si
permeable base
transistors
41
A Gruhle
and P
A Badoz
CNET, Meylan. France
Contents
vii
11:45 1C3
A permeable
base transistor
on Si(łOO)
with implanted
CoSiî-gate
45
A
Schuppen,
S
Mantl,
L
Vescan
and H
Lüth
Institut
für Schicht- und lonentechnik, Jülich,
W Germany
12:00 1C4
A novel compact model description of reverse-biased diode
characteristics including tunnelling
49
GAM Hurkx,
H
С
de
Graaff,
W
J
Kloosterman
and M P G
Knuvers
Philips Research Laboratories, Eindhoven, The Netherlands
12:15
LUNCH
MONDAY AFTERNOON SESSION
2
Session 2IP room Bl: Invited Paper
13:30
2IP1
Compositional analysis of
submicron
silicon in one, two and three
dimensions
53
CHill
Plessey Research Caswell Ltd, Towcester, UK
Session
2
A room Bl: Silicon Processing I
14:15
2A1
titan-rta: a 2D integrated equipment and process model for
simulation of rapid thermal processing
61
S K
Jonest
and
A Gerodolleţ
t
Plessey Research Caswell Ltd, Towcester, UK, JCNET, Meylan,
France
14:30
2A2
Reflectivity measurements in a rapid thermal processor: application to
suicide formation and solid phase regrowth
65
J-M Dilhac.
N
Nolhier and
C Ganibal
Laboratoire d Automatique et d Analyse des Systèmes du CNRS,
Toulouse. France
14:45
2A3
Temperature non-uniformities in a silicon test square during rapid
thermal processing
69
A G
O NeilR
D
Boyst
S K
Jones* and
С
Hill*
t
University of Newcastle-upon-Tyne. UK.
J
Plessey Research
Caswell Ltd. Towcester, UK
viii Contents
15:00
2A4
Prevention of boron penetration from p+ poly gate by RTN produced
thin gate oxide
73
Τ
Morimoto,
H S
Momose,
К
Yamabe and
H Iwai
ULSI Research Center, Toshiba Corporation, Kawasaki, Japan
15:15
2A5
Formation of (TixW, v) Si2/(Ti,W, V)N contacts by rapid thermal
silicidation
77
H
Norströmt,
К
Maext,
J
Vanhellemontt,
G
Brijst, W
Vandervorst
and U SrnithJ
tIMEC,
Leuven,
Belgium,
% Royal Institute
of
Technology,
Kista,
Sweden
15:30
TEA
16:00
2A6
Contact-related effects on junction behaviour
8
І
M L
Polignano and
N
Circelli
SGS
—
Thomson Microelectronics,
Agrate MI,
Italy
16:15
2A7
A new improved electrical vernier to measure mask misalignment
85
D
Morrow,
A J
Walton,
W
R
Gammie,
M
Fallon,
J T
M Stevenson
and R J
Holwill
University of Edinburgh, UK
16:30
2A8
New aspects of intrinsic
gettering
for
CCD
¡magers
89
N
A Sobolev, I Yu Shapiro,
V I Sokolov
and
E D
Vasilyeva
Ioffe Institute, Academy of Sciences of the USSR, Leningrad, USSR
16:45
2A9
Direct observation of the mask edge effect in boron implantation
93
L Gong, J
Lorenz
and
H Ryssel
Fraunhofer Arbeitsgruppe für Integrierte Schaltungen, Erlangen,
W Germany
17:00 2A10
In Situ
cleaning of silicon wafers for selective epitaxial growth
(SEG)
97
M R Goulding, P Kightley, P D
Augustus and
С
Hill
Plessey Research Caswell Ltd, Towcester, UK
17:15
2АП
Properties of IVIetal-SiOj-Si diodes on HF/ethanol cleaned silicon
substrates*
K Kassmi, J L
Prom,
F Gessin and G Sarrabayrouse
Laboratoire d Automatique et d analyse des Systèmes, Toulouse,
France
*
Paper
not available at time of going to press
Contents ix
17:30 2A12
Complementary silicon JFETs using novel ultra-shallow gate junctions
101
Ö
Grelsson,
A Söderbärg
and
U
Magnusson
University of Uppsala, Sweden
Session 2B room C4: Compound Device Structure and Technology
14:15
2B1
Submicron pseudomorphic
Alo.2Gao.8As/I1io.25Gao.75 As-HFET made by
conventional optical lithography for microwave circuit applications
above
100
GHZ
105
H
Meschedef
,
J
Kraust,
R
Bertenburgf
,
W
Brockerhofff
,
W
Prosít,
К
Heimet
Η
Nickeis,
W
Schlapp§ and
R
Lösch§
t Univrersität
-GH- Duisburg,
W Germany,
ţRWTH-Achen,
Institut
für Halbleitertechnik, Aachen, W
Germany,
§
Deutsche
Bundespost Telekom,
Darmstadt, W Germany
14:30
2B2
High electron density and mobility InGaAs/InAlAs modulation doped
structures grown on InP
109
F
Gueissaz,
R
Houdré
and
M Ilegems
Institut de Micro-Optoélectronique, et Ecole Polytechnique
Fédérale, Lausanne,
Switzerland
14:45
2B3
Surface
Characteristics of
plasma
treated WNJGaAs
Contacts
from
С-
V Measurements
11
3
P E Bagnolit, A Paccagnellat, A Callegari§ and F
Fantini
||
t
University of Pisa, Italy,
%
University of
Padova,
Italy,
şi.B.M.,
T J
Watson Research Center, NY, USA, ||
Scuola Superiore
S.
Anna,
Pisa. Italy
15:00
2B4
Gate technologies for AIInAs/InGaAs HEMTs
117
T D
Hunt,
J
Urquhart,
J
Thompson,
R
A Davies and
R H
Wallis
Plessey Research Caswell Ltd, Towcester, UK
15:30
TEA
16:00
2B5
A parametric investigation of the reactive ion etching of InP in
CH4/H2
plasmas using response surface methodology
121
D J
Thomas and
S J
Clements
STC Technology Ltd, Harlow. UK
χ
Contents
16:15
2Β6
Effects of the passivation process on the electrical characteristics of
Gain As planar
photodiodes
125
F
Ducroquetf,
G
Guillott,
J C
Renaudţ
and A Nouailhat§
t
Laboratoire de Physique de la Matière, Villeurbanne, France,
JCNET, Bagneux, France, §CNET, Meylan, France
16:30
2B7
The application
of selective electroless plating for microelectronics
applications
129
С
NiDheasunaf,
T
Spaldingt and
A
MathewsonJ
f
University College, Cork, Ireland,
%
National Microelectronics
Research Centre, Cork, Ireland
16:45
2B8
p
-Туре
AuMn ohmic contact on Ga As: integration in a HBT processing
technology
133
С
Dubon-Chevallier,
A M
Duchenois,
A C Papadopoulo, L Bricard,
F Héliot
and
P
Launay
CNET. Bagneux, France
Session 2C room
ВІЗ:
Bulk
MOS
devices and circuits
14:15
2C1
A fast method of parameter extraction for
MOS
transistors
137
P R
Karlsson
and
K O Jeppson
Chalmers
University of Technology,
Göteborg,
Sweden
14:30
2C2
A charge and capacitance model for modern MOSFETs
141
T
Smedes and
F M
Klaasen
Eindhoven University of Technology, The Netherlands
14:45
2C3
Electron velocity overshoot in sub-micron silicon
MOS
transistors
145
P J
H
Elias,
Th
G van de
Roer
and F M
Klaassen
Eindhoven University of Technology, The Netherlands
15:00
2C4
New short-channel effects on Nitrided Oxide gate MOSFETs
149
H S
Momose.
T
Morimoto,
S
Takagi,
К
Yamabe,
S
Onga and
H Iwai
U
LSI Research Center, Toshiba Corporation, Kawasaki, Japan
15:15
2C5
Analytical model for circuit simulation with quarter micron MOSFETs:
Subthreshold characteristics
153
M
Miura-Mattauseh and
H
Jacobs
Siemens
AG.
Munich.
W
Germany
15:30
TEA
Contents xi
16:00 2C6
Small-signal modelling of MOSFET for circuit design applications
157
V
Altschul,
E
Finkman and
D
Lubzens
Technion Israel Institute of Technology, Haifa, Israel
16:15
2C7
Numerical simulation of
MOS
devices with non-degenerate gate
161
Ρ
Habaš
and
S Selberherr
Institute for Microelectronics, Vienna, Austria
16:30
2C8
Series resistance effects on
EPROM
programming
165
R Bez, D
Cantarelli.
P
Cappelletti, A Maurelli
and L
Ravazzi
SGS-Thomson
Microelectronics,
Agrate, MI,
Italy
16:45
2C9
A flash
EEPROM
cell scaling including tunnel oxide limitations
169
К
Yoshikawat.
S
Morif,
E
Sakagamit,
N
AriJ,
Y
Kanekot
and
Y Oshimat
t
Semiconductor Device Engineering Laboratory, Toshiba
Corporation, Kawasaki, Japan,
J
Toshiba Microelectronics
Corporation, Kawasaki, Japan
17:00
2C10
A new
0.5
μια2
DRAM cell with internal charge gain investigated by 2D
transient device simulation
173
R
Richtert,
К
E
Ehwaldf,
В
Heinemannt,
W
E Matzket,
H Gajewskiî and
W Winklert
t
Institute for Physics of Semiconductors, Academy of Sciences of the
GDR. Frankfurt, GDR,
%
Karl-Weierstrass-Institute of
Mathematics, Academy of Sciences of the GDR, Berlin, GDR
17:15
2СП
A novel flash erase
EEPROM
memory cell with asperities aided erase
177
AAM
Amin
King Fahd University of Petroleum and Minerals, Dhahran, Saudi
Arabia
TUESDAY MORNING SESSION
Session
ЗІР
room Bl: Invited Paper
09:00
31P1
Circuit level models for VLSI components
181
F M Klaassen
Philips Research Laboratories, Eindhoven, The Netherlands
xii Contents
Session
ЗА
Room
Bl: Silicon Processing
II
10:00
3A1
Non-destructive 2D
doping
profiling by the numerical inversion of
CV
measurement
193
G J L
Ouwerling and
M Kleefstra
Delft University of Technology, The Netherlands
10:15
3A2
Low Leakage current evaluations for process characterizations
197
P
Girard,
В
Pistoulet and
P
Nouet
Laboratoire d Automatique et de Microélectronique de Montpellier,
France
10:30
COFFEE
11:00
3A3
Computer simulation
of oxygen precipitation in CZ-silicon during
rapid thermal anneals
201
M Schremst, P
Pongratzţ,
M
Budilt,
H
W
Pötzlt,
J. Hage§,
E Guerrero§ and D Huber§
t
Institut für Allgemeine Elecktrotechnik und Elektronik,
Vienna,
Austria,
% Institut für Angewandte Physik,
Vienna, Austria,
§ Wacker-Chemitronic GmbH, Burghausen,
W Germany
11:15 3A4
Simulation
of arsenic and boron diffusion during rapid thermal
annealing in silicon
205
M
Heinrich,
M Budil and H
W
Pötzl
Institut für Allgemeine Elecktrotechnik und Elektronik,
Vienna,
Austria
11:30 3A5
An
Improved model of plasma etching including temperature
dependence: comparison between simulation and experimental results
209
A Gérodolle, J
Pelletier
and
S Drouot
CNET, Meylan, France
11:45
3A6
Simulation of a Polysilicon LPCVD Reactor
213
Ch
Hopfmann,
J f Ulacia F,
and
Ch
Werner
Siemens
AG,
Munich,
W
Germany
12:00
3A7
Channeling of boron in silicon: experiments and simulation
217
С
Hoblert,
H
Pötzlt,
R Schorkt J
Lorenz
t S Gara§ and G
Stingeder§
t
Institut für Allgemeine
Elecktrotechnik
und Elektronik,
Vienna,
Austria,
% Fraunhofer-Arbeitsgruppe für Integrierte Schaltungen,
Erlangen,
W Germany,
§ Institut für Analyusche Chemie, Technische
Universität,
Vienna, Austria
Contents xiii
12:15 3A8
Towards the limit of ion implantation and rapid thermal annealing as a
technique for shallow junction formation
221
J L
Altript,
AGR
Evanst,
J R
Loganî and
C Jeynes§
f
University of Southampton, UK,
%
Lucas Automotive Ltd, Soihull,
UK,
§
University of Surrey, Guildford, UK
Session 3B Room C4: GaAs
FET
Structures
10:00
3B1
A two-dimensional approach to the noise simulation of GaAs mesfets
225
G Ghione
Politecnico
di Milano,
Italy
10:15
3B2
3D
Integration of GaAs MESFET and varactor diode for a vco-MMic
229
M
Josepht,
В
Rothf,
F Scheffert, H Meschedef, A
Beyerf and
K Heimeí
t Halbleiteriechnik/Halbleiter
technologie,
University of
Duisburg,
W
Germany,
% Institut für Halbleitertechnik, Aachen,
W Germany
10:30
COFFEE
11:15
ЗВЗ
High performance
O-5/ím
GaAs MESFET for MMIC applications
233
A
Belache
and
S Gourrier
Laboratoires d Electronique
Philips, Limeil-Brevannes, France
11:30
3B4
GaAs
FET
and HFET on InP substrate
237
A Clei,
R
Azoulay,
N
Draida,
S
Biblemont and
С
Joly
CNET. Bagneux, France
11:45
3B5
Analysis of the breakdown phenomena in GaAs MESFETs
241
J
Ashwortlrî
and
P
LindorferJ
t
Siemens
AG.
Munich,
W Germany,
J
TU
Vienna,
Austria
Session
ЗС
Room
ВІЗ:
Phenomena in Advanced
MOS
Structures
10:00
3C1
Dynamic hot-carrier stress on
submicron
n-
and p-channel transistors
245
С
Bergonzoni.
G
Dalla Libera
and
A
Nannini
SGS-Thomson Microelectronics,
Agrate MI,
Italy
xiv Contents
10:15 3C2
Hot-carrier experiments on scaled NMOS transistors
249
R
Woltjer,
G M
Paulzen,
P H
Woerlee,
САН
Juffermans
and
H
Lifka
Philips Research Laboratories,
Eindhoven, The Netherlands
10:30
COFFEE
11
:00 3C3
Noise characterisation of Silicon
MOSFETS
degraded by F-N injection
253
С
Nguyen-Due,
G
Ghibaudo and
F
Balestra
Laboratoire de Physique des Composants à Semiconducteurs,
ENSERG, Grenoble, France
11:15
3C4
Hot-carrier-induced degradation in short-channel silicon-on-insulator
MOSFETS
257
T
Ouissef
,
S Cristoloveanut, G Reimbold§ and G Borelt
f Thomson-TMS,
Grenoble, France,
%
Laboratoire de Physique des
Composants à Semiconducteurs, Grenoble, France,
ŞLETl-CENG,
Grenoble, France
11:30
3C5
Study of the enhanced hot-electron injection in split-gate transistor
structures
261
J
Van
Houdt,
P
Heremens,
J S
Witters,
G. Groeseneken
and
H E
Maes
IM
EC,
Leuven,
Belgium
11:45
3C6
Electron conduction and charge trapping behaviour of SiO2 prepared by
plasma anodisation
265
J
F
Zhangt,
P
Watkinsont,
S
Taylort.
W
Ecclestont and
N D
Youngî
+
University of Liverpool. UK,
%
Philips Research Laboratory
Redhill
UK
12:00
3C7
A study of multiplication-induced breakdown in buried-channel p-
MOSFETs
269
T
Skotnicki.
G
Merckel and A Merrachi
CNET, Mevlan. France
Contents xv
12:15 3C8
Electrical characterization of ferroelectric thin films for integration
into VLSI
273
D
M
Swanston,
D J
Johnson,
D T
Amm,
E Griswold and
M Sayer
Queen s University,
Kingston, Canada
12:30
LUNCH
TUESDAY AFTERNOON SESSION
Session 4IP room
Bl:
Invited Paper
13:30
4IP1
Recent trends in multilayer process simulation for
submicron
technologies
277
A Poncét,
A Gérodolle
and
S
Martin
CNET, Meyan, France
Session 4A room Bl: Hot Carriers in
MOS
Devices
14:15
4A1
Comparison of hot-carrier degradation in n- and p-MOSFETs with
various nitride-oxide gate films
287
H
Iwai,
H S
Momose,
T
Morimoto,
S
Takagi and
К
Yamabe
U
LSI Research Centre, Toshiba Corporation, Kawasaki, Japan
14:30
4A2
Duty cycles in digital logic applications: a realistic way of considering
hot-carrier reliability
291
W
Weber,
M Brox, T Kiinemund, D
Schmitt-Landsiedel, Q. Wang
Siemens
AG,
Munich,
W
Germany
14:45
4A3
Annealing of fixed oxide charge induced by hot-carrier stressing
295
M
Brox and
W
Weber
Siemens
AG,
Munich,
W
Germany
15:00
4A4
Gate oxide integrity and hot-carrier degradation of TaSi2 P+ polycide
gate mosfets
299
U Schwalke. W
Hänsch, M
Kerber,
A Lill and
F Neppl
Siemens
AG,
Munich.
W Germany
xvi Contents
15:15 4A5
The effects of gate and drain biases on the stability of low temperature
poly-Si TFTs
303
N D
Young and A Gill
Philips Research Laboratories,
Redhill,
UK
15:30
TEA
16:00
4A6
Optimisation of a
5
nm ONO-multilayer-dielectric for
64
Mbit
DRAMs 307
A
Spitzer,
H
Reisinger and
W
Hönlein
Siemens
AG,
Munich,
W
Germany
16:15
4A7
Optimised and reliable drain structure for
0.5
μηι
n-channel devices
311
G Guegan, G
Reimbold
and
M Lerme
D
LETI CENG,
Grenoble, France
16:30
4A8
The use of a buried lightly doped drain (bledd) for improved nmos
hot-carrier reliability*
K J
Barlow
Plessey Research Caswell Ltd, Northants, UK
16:45
4A9
Simulation of SOI-like kink effects in a Horseshoe-Drain MOSFET for
їбМ
and 64M DRAM applications
315
R
Subrahmanyan,
M
Orlowski and
H Kirsch
Motorola Inc., Austin,
TX, USA
Session 4B room C4: Compound Semiconductor Symposium
14:15
4BIP1
The future of epitaxy
319
P
Balk
Delft University of Technology, The Netherlands
14:45
4BIP2
Directions for optoelectronic circuits§
607
J R
Hayes,
J
Gimlett, W-P Hong, G-K Chang,
J B D
Soole and
R
Bhat
Bellcore. Red Bank, NJ, USA
15:15
Discussion
*
Paper not available at time of going to press
§
Paper submitted late
Contents xvii
15:30
TEA
16:00 4BIP3
GalnAs-based
transistors and circuits for millimetre-wave applications
D
Pons
and
Ρ
Briere
Thomson-CSF, Paris, France
16:30
4BIP4
High packing density techniques for cost effective multifunction GaAs
mmics
327
A A Lane and
F A
Myers
Plessey Research Caswell Ltd, UK
17:00
Discussion
Session 4C room
ВІЗ:
Silicon Bipolar Processing
14:15
4C1
2D Computer simulation of emitter resistance in presence of
interfacial
oxide break-up in polysilicon emitter bipolar transistors
333
J
S
Hamelt,
D J
Roulstonf
, Ρ
AshburnJ,
D Gold§ and
C R
Sel
vakumart
t
University of Waterloo, Ontario, Canada,
ţ
University of
Southampton, UK,
§
University of Oxford, UK
14:30
4C2
Tunnelling in implanted emitter-base junctions in a low-power
UHF
process
337
В
Schlicht
and
L
Strobel
Philips GmbH, Hamburg,
W
Germany
14:45
4C3
Low frequency noise of npn/pnp polysilicon emitter bipolar transistors
341
N
Siabi-Shahrivar,
W
Redman-White,
P
Ashburn and I Post
University of Southampton, UK
15:00
4C4
Small geometry effects in CMOS compatible self-aligned etched-
polysilicon emitter bipolar transistors
345
G
Giroult-Matlakowskit, A Martyf,
N
DegorsJ, A ChantreJ and
A NouailhatJ
+
Motorola Semiconductor, Toulouse, France,
{
CNET, Meylan,
France
*
Paper not available at time of going to press
xviii Contents
15:15 4C5
The application of a selective implanted collector to an advanced
bipolar process
349
M C
Wilson
Plessey Research Caswell Ltd, Towcester, UK
15:30
TEA
16:00
4C6
SiC pn structures grown by container-free LPE (CF lpe) and semi¬
conductor devices based on these structures
353
V A Dmitriev, Ya V Morozenko,
A M Streľchuk, V E Chelnokov
and A E Cherenkov
loffe
Institute, Academy of
Sciences
of the USSR, Leningrad, USSR
16:15
4C7
The application of limited reaction processing to the deposition of
silicon carbide layers
357
F H Ruddell, D W McNeill, B M
Armstrong
and H S Gamble
Queen s University,
Belfast,
UK
WEDNESDAY MORNING SESSION
Session
51
P
room Bl: Invited Paper
09:00
51P1
Degradation and wearout of thin dielectic layers during charge
injection
361
M M
Heyns
IM
EC,
Leuven,
Belgium
Session 5A room Bl
:
Silicon Bipolar and Power Devices
10:00
5A1
Measurement and Simulation of degradation effects in high voltage
DMOS devices
369
P
Dickinger,
G
Nanz and
S Selberherr
Institute for Microelectronics, Technical University Vienna, Austria
10:15
5A2
Technology and design of
SIPOS
films used as field plates for high
voltage planar devices
373
D
Jaumet,
G
CharitatJ, A Pey re-La
vignet
and
P R
osseli
t
Motorola Semiconductors, Toulouse, France,
J
Laboratoire
ďAutomatique
et d Analyse des Systèmes, Toulouse, France
10:30
COFFEE
Contents xix
11:00 5A3
High-speed radiation-hardened ECL circuits on bonded SOI wafers
377
К
Ueno,
M Kawano
and
Y Arimoto
Fujitsu Ltd, Kawasaki, Japan
11:15
5A4
Epitaxial
regro
wth in double-diffused polysilicon emitters
381
J D
Williamst,
P
Ashburnt,
N
E
Moisewitschf,
D P
GoldJ,
J
Whitehurstţ,
G R
Bookerţ
and G R
Wolstenholmet
t
University of Southampton, UK,
%
University of Oxford, UK
11:30
5A5
Sidewall effects in
submicron
bipolar transistors
385
S
Decoutere,
L
Deferm,
С
Claeys and
G Declerck
IM EC,
Leuven,
Belgium
11:45
5A6
BASIC II: A super self-aligned technology for high-performance bipolar
applications
389
A Pruijmboom, ACL
Jansen,
H G R
Maas,
P H
Kranen,
R
A van
Es,
R
Dekker
and J
W
A van
der Velden
Philips Research Laboratories, Eindhoven, The Netherlands
12:00
5A7
Silicon-based pseudo-heterojunction bipolar transistors
393
Z
A Shafi and
P
Ashbum
University of Southampton, UK
12:15
5A8
A
12
V BICMOS technology for mixed analog-digital applications, with
high performance vertical pnp
397
C Mallardeau, P
Keen, A Monroy,
J C
Marin, F Dell Ova,
P A
Brunei, D
Celi and
M Roche
SGS-Thomson Microelectronics,
Grenoble, France
Session 5B
room C4: Optical Properties and
Devices
10:00
5B1
MBE HEMT-compatible diode lasers
401
J
Ebner,
J E
Lary,
G W
Eliason and T K Plant
Oregon State
University, USA
10:15
5B2
Optical characterisation
of InGaAs/InP and InGaAs/InGaAsP MQW
structures for optoelectronic applications
405
К
Wolter, R Schwedler,
F
Reinhardt,
R Kersting, X Q
Zhou,
D
Grützmacher
and H Kurz
Institute
of Semiconductor
Electronics,
Aachen,
W Germany
10:30
COFFEE
xx Contents
11:00 5B3
Strongly directional emission from AlGaAs/GaAs light emitting
diodes
409
A
Köckt,
E
Gornikt,
M
Hauser!
and
W
Beinstinglî
f
Walter Schottky
Institut, TU
Munich,
W
Germany,
%
Institut
für
Experimentalphysik, Universität Innsbruck,
Austria
11:15 5B4
Detection of Near
ir
radiation by SiGe material
413
В
Sopko,
J
Pavlu, I Procházka
and I
Macha
Technical University, Prague, Czechoslovakia
11:30
5B5
In-line control with scanning photoluminescence of infrared
photodiode
arrays fabricated on lattice mismatched InGaAs/InP heterostructures*
S
Krawczykt,
К
Schohef
,
С
Klingelhofert,
В
Vilotitcht
С
LenobleJ,
M
Villardt X HugonJ,
D
Regaud§,
F
Ducroquet§
t
Laboratoire d Electronique, Ecole Centrale de Lyon, France,
%
Thomson CMS, St
Egreve,
France,
§
Laboratoire de Physique de la
Matière, Lyon, France
11:45
5B6
High-reliability semi-conductor
laser
amplifiers
417
S
J
Fisher,
C P Skrimshire, R
N Shaw,
J R Farr, P C Spurdens,
H J Wickes and
W
J
Devlin
British
Telecom Research Laboratories,
Ipswich, UK
12:00
5B7
Band to band absorption coefficients in heavily doped Si and SiGe
421
A Nathant,
S C Jain+, D R Brigliot, J M McGregort
and
D J
Roulstont
f
University of Waterloo, Ontario, Canada,
%
Oxford University, UK
Session 5C Room
ВІЗ:
Silicon on Insulator II
10:00
5C1
Design considerations for
0·5
micron ultra thin film sub-micron SOI
transistors by two-dimensional simulation
425
G
A Armstrongf,
W
D
Frencht and
J R
DavisJ
tQueen s University, Belfast, UK,
J
British Telecom Research
Laboratories, Ipswich, UK
10:15
5C2
The influence of substrate bias fixed charge in the buried insulator on
the gain of the parasitic bipolar inherent in silicon-on-insulator
MOSFETs
429
L J
McDaidt,
S
Hallt,
W Ecclestont
and J
С
AldermanJ
+
University of Liverpool, UK, JPlessey Research Caswell Ltd,
Towcester, UK
*
Paper not available at time of going to press
Contents xxi
10:30
COFFEE
11:00 5C3
Single-transistor latch induced degradation in thin-film SOI MOSFETs:
implications for sub-micron SOI MOSFETs
433
R J T
Bunyant,
M J Urent, L McDaidJ, S
Hallt,
W
Ecclestonî,
N
Thomas§ and J R Davis§
t
Royal Signals
and
Radar Establishment,
Great
Malvern,
UK,
I University of Liverpool, UK,
§
British Telecom Research
Laboratories, Ipswich, UK
11:15
5C4
Intrinsic gate capacitances of SOI MOSFETs: Measurement, modelling,
floating substrate effects
437
D
Flandret,
F
Van
de
Wielet, PGA Jespersf and
M Haondî
f
Université Catholique de Louvain,
Belgium,
%
CNET, Meylan,
France
11:30
5C5
Identification
and characterisation of
noise sources in
SIMOX MOSFETs
441
T
Elewat,
В
Boukrisst, H HaddaraJ, A Chovetf and
S Cristoloveanut
t
Laboratoire de Physique des Composant à Semiconducteurs,
Grenoble, France,
%
Ain-Shams
University, Cairo, Egypt
11:45
5C6
Improvement of output impedance in SOI MOSFETs
445
M
-Н
Gao,
J-P Colinge,
S
-Н
Wu and
С
Claeys
IMEC,
Leuven,
Belgium
12:00
5C7
Temperature behaviour of CMOS devices built on
SIMOX
substrates
449
J
Beiz,
G
Burbach,
H
Vogt and
W
Zimmermann
Fraunhofer Institute
of Microelectronic Circuits and Systems,
Duisburg, W
Germany
12:15
5C8
Thin
SIMOX SOI
material for half-micron CMOS
453
H
Lifka and
P H
Woerlee
Philips Research Laboratories, Eindhoven, The Netherlands
12:30
LUNCH
WEDNESDAY AFTERNOON
Conference excursion and banquet
xxii Contents
THURSDAY MORNING SESSION
Session 6IP room Bl: Invited Papers
09:00
6IP1
MicrocontaminationS
625
Τ
Ohmi
and
Τ
Shibata
Tohoku University, Japan
10:00
6IP2
Nanometric structures on compound semiconductors*
C D
Wilkinson
University of Glasgow, UK
10:45
COFFEE
Session 6A Room Bl
:
DRAM Technology
11:15
6A1
A new stacked capacitor cell for
64
Mbit
DRAMs 457
Cheon
Soo
Kim, Jin Ho Lee, Kyu Hong Lee, Dae Yong Kim, Jin Hyo
Lee and Chung
Duk Kim
Electronics and Telecommunication Research Institute, Daejeon,
Korea
11:30
6A2
Stacked capacitor cell technology for
16м
DRAM using double self-
aligned contacts
461
M
Fukumoto,
Y
Naito,
К
Matsuyama,
H
Ogawa,
K Matsuoka,
T
Hori,
H Sakai,
I
Nakao,
H
Kotani,
H Iwasaki and M Inoue
Semiconductor
Research Centre, Matsushita Electric
Industry Co
Ltd, Osaka, Japan
11
:45 6A3
Buried stacked capacitor cells for 16M and 64M drams
465
J
Dietl,
L
DoThanh,
K H
Küsters,
L Kusztelan, H M Miilhoff,
W
Müller
and
F
X
Stelz
Siemens AG.
Munich.
W Germany
12:00 6 A4
Coupling of different leakage paths between trench capacitors
469
W
Bergner
and
R
Kircher
Siemens
AG,
Munich,
W
Germany
*
Paper not avilable at time of going to press
§
Paper submitted late
Contents xxiii
Session 6B
room
C4: Heterojunction Bipolar Technology
11:15 6B1
Temperature dependence of DC characteristics of Si/SiGe
heterojunction bipolar transistors
473
A S R
Martin,
M A
Gell,
A A
Reeder,
D J
Godfrey,
M E
Jones,
C J
Gibbings and
C G Tuppen
British
Telecom Research Laboratories,
Ipswich, UK
11:30
6B2
Self aligned
Si/SiGe heterojunction
bipolar
transistors
grown by
molecular beam epitaxy on diffused
n
+-buried layer structures
477
P
Narożny,
D
Köhlhoff,
H
Kibbel and E
Kasper
Daimler-Benz Research Centre,
Ulm, W
Germany
11:45
6B3
Fabrication and characteristics of a MBE-grown InAlAs/InGaAs
heterojunction bipolar transistor using an embedded collector
481
L
M Su, H
Künzel,
R
Gibis,
G Mekonnen,
W Schlaak and
N
Grote
Heinrich-Hertz-Institut
für Nachrichtentechnik
Berlin GmbH, W
Germany
12:00
6B4
Performance
of AIGaAs/GaAs heterostructure
bipolar
transistors
growa by MOVPE
485
В
Willen,
D
Haga and
G Landgren
Swedish Institute of Microelectronics,
Kista,
Sweden
Session 6C room
ВІЗ:
Physical Processes in Silicon Device Structures
11:15
6C1
A Monte Carlo simulator including generation-recombination
processes
489
L
Reggianif,
T
Kuhnt, L
Varanit,
D Gasquet|, J C
Vaissiereţ
and
J P
NougierJ
+
Universita
di
Modena, Italy,
%
Université des
Sciences
et Technique
du Languedoc. Montpellier, France
11:30
6C2
Treatment
of thermomagnetic effects in semiconductor device
modelling
493
S
Rudin
and
H
Bakes
Institute of Quantum Electronics,
ΕΤΗ
Zürich,
Switzerland
11:45
6C3
On the modelling of mobility in silicon
MOS
transistors
497
A Emrani,
G
Ghibaudo and
F
Balestra
Laboratoire de Physique des Composants à Semiconducteurs,
ENSERG, Grenoble, France
xxiv Contents
12:00 6C4
The hysteresis behaviour of silicon
p
-η
diodes at liquid helium
temperature
501
В
Dierickx,
E
Simoen,
L
Deferm and
C Claeys
IM EC,
Leuven,
Belgium
12:15
6C5
Influence of generation-recombination process on transient transport
in p-type silicon at
77
K*
N Nemar, J
С
Vaissiere,
J P
Nougier
Université Montpellier
II,
Sciences et Techniques du Lanquedoc,
Montpellier, France
12:30
LUNCH
Session 7IP
room BI:
Invited
Paper
13:30
7IP1
Recent trends in InP-based optoelectronic components
505
О
Hildebrand
SEL
Research Centre, Stuttgart,
W
Germany
Session
7
A room Bl: Silicon Circuits
14:15
7A1
A high-energy ion implanted BICMOS process with compatible
EPROM
structures
515
R C M
Wijburg,
G J Hemink, J Middelhoek and H
Wallinga
University of Twente,
Enschede,
The Netherlands
14:30
7A2
A high performance VLSI structure-SOi/SDB complementary buried
channel
mos
(cbcmos) ic
519
Q-Y
Tong,
Х
-L
Xu, H-Z
Zhang
Southeast University, Nanjing, China
14:45
7A3
A well concept for field-implant free isolation and width independent
n-MOSFET threshold and reliability
523
Ch
Zeiler,
С
Mazure,
A Lill
and
M
Kerber
Siemens
AG,
Munich,
W
Germany
15:00
7A4
Simulation of
EPROM
writing
527
С
Fiegnat,
F
Venturit,
M
MelanotteJ,
E
Sangiorgi§ and
В
Riccòt
t
DEIS University of Bologna, Italy,
%
SGS-Thomson
Microelectronics,
Agrate MI,
Italy,
§
University of
Udine,
Italy
15:15
TEA
*
Paper not available at time of going to press
Contents xxv
15:45 7A5
Field isolation and active devices for
16
Mbit drams
531
Н
-M
Miihlhoff,
J Dietl, P
Küpper
and
R Lemme
Siemens
AG,
Munich,
W
Germany
16:00
7A6
Dimensional characterisation of poly buffer LOCOS in comparison with
suppressed LOCOS
535
NAH
Wils,
P
A van
der Plas
and
A H Montrée
Philips Research Laboratories, Eindhoven, The Netherlands
16:15
7A7
Modelling and simulation of silicon-on-sapphire MOSFETs for analogue
circuit design
539
R
Howest,
W
Redman-Whitet,
K G Nicholst, S J
MurrayJ and
P J
Мо1е§
t
Southampton University, UK,
%
Marconi Electronic Devices Ltd,
Lincoln, UK, §GEC Hirst Research Centre, Wembley, UK
16:30
7A8
ELSIMA: ELDO short-channel IGFET model for analog applications
543
T
Pedron and
G Merckel
CNET, Meylan, France
16:45
7A9
A fully modular
1
џт
CMOS technology incorporating
EEPROM,
EPROM
and interpoly capacitors
547
P J Cacharelis, M J
Hart,
G R Wolstenholme, R D
Carpenter,
I
F
Johnson and
M H Manley
National Semiconductor Corporation, Santa Clara, CA, USA
Session 7B room C4: Physics of Optical and Related Devices
14:15
7B1
Optical switches and heterojunction bipolar transistors in InP for
monolithic integration
551
N
Shaw,
P J
Topham,
M J
Wale
Plessey Research Caswell Ltd, Towcester, UK
14:30 7B2
Numerical modelling based comparison of the submicrometre HI—V
compounds MESFET s performance
555
V Ryzhii and G. Khrenov
Institute of Physics and Technology, USSR Academy of Sciences,
Moscow, USSR
14:45
7B3
Small signal analysis of resonant tunnel diodes in the bistable mode
559
A Zarea,
A Sellai, M S
Raven,
D P
Steenson. J M Chamberlain,
M
Heni
ni
and O H
Hughes
University of Nottingham. UK
xxvi Contents
15:00 7B4
Planar InP/InGaAs avalanche
photodiodes
fabricated without a guard
ring using silicon implantation and two-stage atmospheric pressure
MOVPE
563
MDA
MacBean,
Ρ Μ
Rodgers,
T G Lynch, M D
Learmouth and
R H
Walling
British Telecom Research Laboratories, Ipswich, UK
15:15
TEA
15:45
7B5
Estimation of noise figure for conventional and multilayered avalanche
photodiodes
using the lucky drift model
567
J
S
Marslandt,
R
С
WoodsJ,
С
A
Brownhill*
and
S
GouldJ
t
University of Liverpool, UK,
%
University of Sheffield, UK
16:00
7B6
lOGbit/s on-chip photodetection with self-aligned silicon bipolar
transistors
571
J
Poppt
and
H
Philipsbornţ
f
Siemens
AG,
Munich,
W Germany,
%
University of
Regensburg,
W Germany
16:15
7B7
A Sensitive MNMOS structure for optical storage
575
M S
Shivaraman and
O Engström
Chalmers University of Technology,
Göteborg,
Sweden
Session 7C room
ВІЗ:
MOS-based Structures and Measurements
14:15
7C1
A new charge pumping procedure to measure Interface trap energy
distributions on MOSFETs
579
G
Van den bosch,
G
Groeseneken,
P
Heremans
and
H E
Maes
IM
EC,
Leuven,
Belgium
14:30
7C2
Interface states extracted from gated diode and charge pumping
measurements
583
F
Hofmann
Siemens
AG,
Munich,
W
Germany
14:45
7C3
Extended static CV -procedure to investigate minority carrier
generation in
MOS
capacitors
587
M
Kerber
and
U
Sehwalke
Siemens
AG.
Munich,
W
Germany
Contents xxvii
15:00 7C4
Local temperature distribution in Si-MOSFETs studied by micro-raman
spectroscopy
591
R
Ostermeirt,
К
Brunnert,
G
Abstreitert and
W
Weberi
t
Walter Schottky
Institut,
Technische Universität,
Munich,
W
Germany,
%
Siemens
AG,
Munich,
W
Germany
15:15
TEA
15:45
7C5
Defects in highly doped silicon investigated by combined current and
capacitance DLTS
595
G I Andersson
and
O Engström
Chalmers University of Technology,
Göteborg,
Sweden
16:00
7C6
A four million pixel
CCD
image sensor
599
T H
Lee,
В С
Burkey
and R P Khosla
Eastman Kodak
Company, Rochester, NY,
USA
16:15 7C7
Unified model of the enhancement-mode
MOS
transistor
603
W J
Kordalski
Technical University of Gdansk, Poland
16:30
END OF CONFERENCE
Author index
633
|
| any_adam_object | 1 |
| author2 | Eccleston, W. |
| author2_role | edt |
| author2_variant | w e we |
| author_corporate | ESSDERC Nottingham |
| author_corporate_role | aut |
| author_facet | Eccleston, W. ESSDERC Nottingham |
| author_sort | ESSDERC Nottingham |
| building | Verbundindex |
| bvnumber | BV004619991 |
| classification_rvk | UP 3100 |
| classification_tum | ELT 340f |
| ctrlnum | (OCoLC)180512768 (DE-599)BVBBV004619991 |
| discipline | Physik Elektrotechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1990 Nottingham gnd-content |
| genre_facet | Konferenzschrift 1990 Nottingham |
| id | DE-604.BV004619991 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:15:04Z |
| institution | BVB |
| institution_GND | (DE-588)3007156-2 |
| isbn | 0750300655 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002838091 |
| oclc_num | 180512768 |
| open_access_boolean | |
| owner | DE-384 DE-91 DE-BY-TUM DE-355 DE-BY-UBR DE-83 |
| owner_facet | DE-384 DE-91 DE-BY-TUM DE-355 DE-BY-UBR DE-83 |
| physical | XXIX, 637 S. Ill., graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| publisher | Hilger |
| record_format | marc |
| spelling | ESSDERC 20 1990 Nottingham Verfasser (DE-588)3007156-2 aut ESSDERC 90 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 organized by the Institute of Physics. ed. by W. Eccleston ... Bristol [u.a.] Hilger 1990 XXIX, 637 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Halbleiterbauelement (DE-588)4113826-0 gnd rswk-swf Festkörperbauelement (DE-588)4154179-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1990 Nottingham gnd-content Festkörperbauelement (DE-588)4154179-0 s DE-604 Halbleiterbauelement (DE-588)4113826-0 s Eccleston, W. edt Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002838091&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | ESSDERC 90 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 Halbleiterbauelement (DE-588)4113826-0 gnd Festkörperbauelement (DE-588)4154179-0 gnd |
| subject_GND | (DE-588)4113826-0 (DE-588)4154179-0 (DE-588)1071861417 |
| title | ESSDERC 90 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 |
| title_auth | ESSDERC 90 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 |
| title_exact_search | ESSDERC 90 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 |
| title_full | ESSDERC 90 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 organized by the Institute of Physics. ed. by W. Eccleston ... |
| title_fullStr | ESSDERC 90 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 organized by the Institute of Physics. ed. by W. Eccleston ... |
| title_full_unstemmed | ESSDERC 90 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 organized by the Institute of Physics. ed. by W. Eccleston ... |
| title_short | ESSDERC 90 |
| title_sort | essderc 90 20th european solid state device research conference nottingham 10 13 september 1990 |
| title_sub | 20th European Solid State Device Research Conference, Nottingham, 10 - 13 September 1990 |
| topic | Halbleiterbauelement (DE-588)4113826-0 gnd Festkörperbauelement (DE-588)4154179-0 gnd |
| topic_facet | Halbleiterbauelement Festkörperbauelement Konferenzschrift 1990 Nottingham |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002838091&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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