Superscalar microprocessor design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Englewood Cliffs, NJ
Prentice Hall
1991
|
| Schriftenreihe: | Prentice Hall series in innovative technology
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXIV, 288 S. graph. Darst. |
| ISBN: | 0138756341 |
Internformat
MARC
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| 100 | 1 | |a Johnson, Mike |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Superscalar microprocessor design |c Mike Johnson |
| 264 | 1 | |a Englewood Cliffs, NJ |b Prentice Hall |c 1991 | |
| 300 | |a XXIV, 288 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Prentice Hall series in innovative technology | |
| 650 | 7 | |a CISC |2 inriac | |
| 650 | 7 | |a MIPS |2 inriac | |
| 650 | 7 | |a Microprocesseurs |2 ram | |
| 650 | 7 | |a R2000 |2 inriac | |
| 650 | 7 | |a RISC |2 inriac | |
| 650 | 7 | |a Rise (Ordinateurs) |2 ram | |
| 650 | 7 | |a architecture flot donnée |2 inriac | |
| 650 | 7 | |a conception microprocesseur |2 inriac | |
| 650 | 7 | |a processeur superscalaire |2 inriac | |
| 650 | 4 | |a Microprocessors |x Design and construction | |
| 650 | 4 | |a Reduced instruction set computers | |
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| 689 | 0 | 0 | |a Superskalarer Mikroprozessor |A f |
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Datensatz im Suchindex
| _version_ | 1804118673902796800 |
|---|---|
| adam_text | Superscalar
Microprocessor
Design
Mike Johnson
Advanced Micro Devices
Prentice Hall, Englewood Cliffs, New Jersey 07632
Contents
Preface xxi
Chapter 1
Beyond Pipelining, CISC, and RISC 1
Chapter 2
An Introduction to Superscalar Concepts 9
2 1 FUNDAMENTAL LIMITATIONS 9
211 True Data Dependencies 10
212 Procedural Dependencies 12
213 Resource Conflicts 13
214 Instruction Parallelism and Machine Parallelism 15
2 2 INSTRUCTION ISSUE AND MACHINE PARALLELISM 17
221 In-Order Issue with In-Order Completion 18
222 In-Order Issue with Out-of-Order Completion 19
223 Out-of-Order Issue with Out-of-Order Completion 21
224 Storage Conflicts and Register Renaming 22
2 3 RELATED CONCEPTS:
VLIW AND SUPERPIPELINED PROCESSORS 24
231 Very-Long-Instruction-Word Processors 25
232 Superpipelined Processors 26
233 Hybrid Techniques 28
2 4 UNRELATED PARALLEL SCHEMES 28
Chapter 3
Developing an Execution Model 31
3 1 SIMULATION TECHNIQUE 32
3 2 BENCHMARKING PERFORMANCE 35
vii
3 3 BASIC OBSERVATIONS ON HARDWARE DESIGN 37
331 The Philosophy of the Standard Processor 38
332 Instruction Parallelism of the Benchmarks 38
333 Machine Parallelism 41
3 4 THE DESIGN OF THE STANDARD PROCESSOR 44
341 Basic Organization 44
342 Out-of-Order Issue 46
343 Register Renaming 48
344 Loads and Stores 50
345 The Performance of the Model 53
3 5 THE REAL PERFORMANCE LIMIT:
PROCEDURAL DEPENDENCIES 54
3 6 BACKGROUND 55
Chapter 4
Instruction Fetching and Decoding 57
4 1 BRANCHES AND INSTRUCTION-FETCH INEFFICIENCIES 57
4 2 IMPROVING FETCH EFFICIENCY 60
421 Scheduling Delayed Branches 61
422 Branch Prediction 63
423 Aligning and Merging 65
424 Simulation Results and Observations 67
425 Multiple-Path Execution 69
4 3 IMPLEMENTING HARDWARE BRANCH-PREDICTION 71
431 Basic Organization 73
432 Setting and Interpreting Cache Entries 73
433 Predicting Branches 75
434 Hardware and Performance Costs 76
4 4 IMPLEMENTING A FOUR-INSTRUCTION DECODER 77
4 5 IMPLEMENTING BRANCHES 81
451 Number of Pending Branches 81
452 Order of Branch Execution 82
453 Simplifying Branch Decoding 83
4 6 REDUCING THE PENALTY OF PROCEDURAL DEPENDENCIES:
OBSERVATIONS 85
Chapter 5
The Role of Exception Recovery 87
5 1 BUFFERING STATE INFORMATION FOR RESTART 87
511 In-Order, Lookahead, and Architectural State 88
512 Checkpoint Repair 89
513 History Buffer 91
514 Reorder Buffer 92
515 Future File 94
viii Contents
5 2 RESTART IMPLEMENTATION AND
EFFECT ON PERFORMANCE 95
521 Mispredicted Branches 96
522 Exceptions 98
523 The Effect of Recovery Hardware on Performance 101
5 3 PROCESSOR RESTART: OBSERVATIONS 102
Chapter 6
Register Dataflow 103
6 1 DEPENDENCY MECHANISMS 105
611 The Value of Register Renaming 107
612 Register Renaming with a Reorder Buffer 110
613 Renaming with a Future File: Tomasulo s Algorithm 110
614 Enforcing Dependencies with Interlocks 112
615 Copying Operands to Avoid Antidependencies 115
616 Partial Renaming 116
617 Special Registers and Instruction Side Effects 119
6 2 RESULT BUSES AND ARBITRATION 120
6 3 RESULT FORWARDING 122
6 4 SUPPLYING INSTRUCTION OPERANDS: OBSERVATIONS 125
Chapter 7
Out-of-Order Issue 127
7 1 RESERVATION STATIONS 129
711 Reservation Station Operation 129
712 Performance Effect of Reservation-Station Size 130
713A Simpler Implementation of Reservation Stations 132
7 2 IMPLEMENTING A CENTRAL INSTRUCTION WINDOW 133
721 The Dispatch Stack 135
722 The Register Update Unit 137
723 Using a Reorder Buffer to Simplify the Central Window 139
724 Operand Buses from a Central Window 142
725 The Complexity of a Central Window 144
7 3 OUT-OF-ORDER ISSUE: OBSERVATIONS 146
Chapter 8
Memory Dataflow 147
8 1 ORDERING OF LOADS AND STORES 148
811 Total Ordering of Loads and Stores 148
812 Load Bypassing of Stores 150
813 Load Bypassing with Forwarding 151
814 Performance of the Load/Store Policy 152
815 Load Side Effects 153
Contents ix
8 2 ADDRESSING AND DEPENDENCIES 154
821 Limiting Address Logic with a
Preaddress Buffer or Central Instruction Window 154
822 Effect of Store-Buffer Size 156
823 Memory Dependency Checking 157
8 3 WHAT IS MORE LOAD/STORE PARALLELISM WORTH? 159
8 4 ESOTERICA: MULTIPROCESSING CONSIDERATIONS 161
8 5 ACCESSING EXTERNAL DATA: OBSERVATIONS 162
Chapter 9
Complexity and Controversy 165
91A BRIEF GLIMPSE AT DESIGN COMPLEXITY 166
911 Allocating Processor Resources 166
912 Instruction Decode 168
913 Instruction Completion 170
914 The Painful Truth 170
9 2 MAJOR HARDWARE FEATURES 171
9 3 HARDWARE SIMPLIFICATIONS 172
9 4 IS THE COMPLEXITY WORTH IT? 175
Chapter 10
Basic Software Scheduling 177
10 1 THE BENEFIT OF SCHEDULING 178
10 1 1 Impediments to Efficient Execution 179
10 1 2 How Scheduling Can Help 179
10 1 3 Is the Benefit Significant? 181
10 2 PROGRAM INFORMATION NEEDED FOR SCHEDULING 182
10 2 1 Dividing Code into ^asic Blocks 182
10 2 2 The Dataflow Graph of a Basic Block 184
10 2 3 The Precedence Graph 184
10 2 4 The Concept of the Critical Path 186
10 2 5 The Resource Reservation Table 187
10 3 RELATIONSHIP OF THE SCHEDULER AND THE COMPILER 187
10 3 1 Interaction of Register Allocation and Scheduling 187
10 3 2 Scheduling During Compilation Versus After Compilation 189
10 4 ALGORITHMS FOR SCHEDULING BASIC BLOCKS 191
10 4 1 The Expense of an Optimum Schedule 191
10 4 2 List Scheduling 193
10 4 3 The Effect of Scheduling Order 196
10 4 4 Other Scheduling Alternatives 197
10 5 REVISITING THE HARDWARE 199
Chapter 11
Software Scheduling Across Branches 203
11 1 TRACE SCHEDULING 205
Contents
11 11A Simple Example of Trace Scheduling 205
11 1 2 Using Compensation Code to
Recover from Incorrect Predictions 208
11 1 3 Trace Scheduling an Entire Program 211
11 1 4 Correctness of Trace Scheduling 212
11 2 LOOP UNROLLING 213
11 2 1 Unrolling to Improve the Loop Schedule 214
11 2 2 Unrolling with Data-Dependent Branches 214
11 3 SOFTWARE PIPELINING 216
11 3 1 Pipelining Operations from Different Loop Iterations 217
11 3 2 Software-Pipelining Techniques 220
11 3 3 Filling and Flushing the Pipeline: The Prologue and Epilogue 225
11 3 4 Register Renaming in the Software-Pipelined Loop 227
11 4 GLOBAL CODE MOTION 229
11 5 OUT-OF-ORDER ISSUE AND
SCHEDULING ACROSS BRANCHES 233
Chapter 12
Evaluating Alternatives:
A Perspective on Superscalar Microprocessors 237
12 1 THE CASE FOR SOFTWARE SOLUTIONS 239
12 1 1 Instruction Formats to Simplify Hardware 239
12 1 2 Instruction Formats for Scheduling Across Branches 242
12 1 3 The Costs and Risks of Software Solutions 244
12 2 THE CASE FOR HARDWARE SOLUTIONS 247
12 2 1 Two Models of Performance Growth 248
12 2 2 Estimating Risks in a Performance-Oriented Design 251
12 2 3 Estimating Risks in a Cost-Sensitive Design 254
12 2 4 Putting Risks in Perspective 257
Appendix
A Superscalar 386 261
A 1 THE ARCHITECTURE 261
A11 Instruction Format 262
A12 Register Dependencies 264
A13 Memory Accesses 265
A14 Complex Instructions 266
A 2 THE IMPLEMENTATION 267
A21 Out-of-Order Microinstruction Issue 268
A22 Overlapping Microinstruction Sequences 269
A23 Superscalar Execution of a RISC Core Instruction Set 271
A 3 CONCLUSION 272
References 273
Index 279
Contents xi
|
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| dewey-raw | 621.39/16 |
| dewey-search | 621.39/16 |
| dewey-sort | 3621.39 216 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| genre | Superskalarer Mikroprozessor gnd |
| genre_facet | Superskalarer Mikroprozessor |
| id | DE-604.BV004539556 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:14:03Z |
| institution | BVB |
| isbn | 0138756341 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002794706 |
| oclc_num | 611665485 |
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| owner_facet | DE-91 DE-BY-TUM |
| physical | XXIV, 288 S. graph. Darst. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| publisher | Prentice Hall |
| record_format | marc |
| series2 | Prentice Hall series in innovative technology |
| spelling | Johnson, Mike Verfasser aut Superscalar microprocessor design Mike Johnson Englewood Cliffs, NJ Prentice Hall 1991 XXIV, 288 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Prentice Hall series in innovative technology CISC inriac MIPS inriac Microprocesseurs ram R2000 inriac RISC inriac Rise (Ordinateurs) ram architecture flot donnée inriac conception microprocesseur inriac processeur superscalaire inriac Microprocessors Design and construction Reduced instruction set computers Superskalarer Mikroprozessor gnd rswk-swf Superskalarer Mikroprozessor f DE-604 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002794706&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Johnson, Mike Superscalar microprocessor design CISC inriac MIPS inriac Microprocesseurs ram R2000 inriac RISC inriac Rise (Ordinateurs) ram architecture flot donnée inriac conception microprocesseur inriac processeur superscalaire inriac Microprocessors Design and construction Reduced instruction set computers |
| title | Superscalar microprocessor design |
| title_auth | Superscalar microprocessor design |
| title_exact_search | Superscalar microprocessor design |
| title_full | Superscalar microprocessor design Mike Johnson |
| title_fullStr | Superscalar microprocessor design Mike Johnson |
| title_full_unstemmed | Superscalar microprocessor design Mike Johnson |
| title_short | Superscalar microprocessor design |
| title_sort | superscalar microprocessor design |
| topic | CISC inriac MIPS inriac Microprocesseurs ram R2000 inriac RISC inriac Rise (Ordinateurs) ram architecture flot donnée inriac conception microprocesseur inriac processeur superscalaire inriac Microprocessors Design and construction Reduced instruction set computers |
| topic_facet | CISC MIPS Microprocesseurs R2000 RISC Rise (Ordinateurs) architecture flot donnée conception microprocesseur processeur superscalaire Microprocessors Design and construction Reduced instruction set computers Superskalarer Mikroprozessor |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002794706&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT johnsonmike superscalarmicroprocessordesign |