VLSI 89: proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989
Saved in:
| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Amsterdam u.a.
North-Holland
1990
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Literaturangaben |
| Physical Description: | XIII, 516 S. Ill., graph. Darst. |
| ISBN: | 0444883444 |
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MARC
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| 245 | 1 | 0 | |a VLSI 89 |b proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 |c ed. by G. Musgrave ... |
| 264 | 1 | |a Amsterdam u.a. |b North-Holland |c 1990 | |
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Record in the Search Index
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| adam_text |
CONTENTS
Preface
v
Organization
vii
Session
1:
Cell Generation
1.1.
Open Integrated Design Environment: Wishful Thinking or
Realistic Goal?
R.
Piloty
3
1.2.
Single-Level Wiring for Cell Compilers
R. Nair
13
1.3.
A Module Generation System of Dense Pseudo-Random Layouts
for Speed-Tuned
MOS
Circuits
Z.-J. Dai, Y.
Sone,
and K.
Asada
23
Session
2:
Processor Architectures
2.1.
ARM3
-
32b RISC Processor with 4Kbyte On-Chip Cache
S.B. Furber, A.R.P. Thomas, H.E. Oldham,
D.W.
Howard,
J.S. Urquhart, and A.R. Wilson
35
2.2.
SPRINT: A Processor for a Parallel Architecture
P.A.
Rounce, K. Chan,
M. Hardie,
and K. Steptoe
45
2.3.
From Chip to System: The SPUR CPU Experience
S.I. Kong,
D.D.
Lee, R.H. Katz, D.A. Hodges, and
D.A. Patterson
55
Session
3:
Simulation and Verification
3.1.
The Ivory Lisp Processor Project
-
Some Experiences with
Big VLSI
N. Weste 67
x
Contents
3.2. SLS: an
Efficient Switch-Level Timing Simulator Using
Min-Max
Voltage Waveforms
A.J. van Genderen
79
3.3.
VERA, a
Rule-Based Verification Assistant for
VLSI Circuit Design
A.P.
Kostelijk
89
Session
4:
Formal Verification and Testing
4.1.
Formally Based System Design
-
Interactive Hardware
Scheduling
M.P. Fourman and E.M. Mayger
101
4.2.
Formal Specification and Verification of Synthesized
MOS
Structures
J.J. Joyce
113
4.3.
Synthesis of Dedicated Controllers for Concurrent Checking
R. Leveugle and G. Saucier
123
4.4.
An Efficient Implementation of the BALLAST Partial
Scan Architecture
R. Gupta, R. Gupta, and M.A.
Breuer 133
4.5.
The BED Concept
—
A Method and a Language for Modular
Test Generation
W. Roth, M. Johansson, and W. Glunz
143
4.6.
Test Expertise for ASICs
M. Crastes
de
Paulet, M.
Karam,
and G. Saucier
153
4.7.
DC Macromodelling of Mixed Signal Integrated Circuits for
Testing Purposes
J.B. Hibbert and A.P. Dorey
163
Session
5:
Synthesis
5.1.
The Relationship between Logic Synthesis and Test
S. Devadas, Hi-Keung Tony Ma, A.R. Newton,
and A. Sangiovanm-Vincentelli
175
5.2.
Synthesis of Multiple Level Logic from Symbolic High-Level
Description Languages
B. Lin and A.R. Newton
187
Contents xi
5.3. CALLAS -
Conversion
of Algorithms to Library
Adaptable Structures
P. Duzy, H.
Krämer,
M. Neher, M.
Piisi, W.
Rosenstiel,
T.
Wecker 197
5.4.
Background Memory
Synthesis for Algebraic Algorithms on
Multi-Processor DSP Chips
I. Verbauwhede, F. Catthoor, J. Vandewalle, and H.
De Man 209
Session
6:
Logic and Timing Optimization
6.1.
Encoding Symbolic Inputs for Multi-Level Logic Implementation
S. Malik, R.K. Brayton, A. Sangiovanni-Vincentelli
221
6.2.
Boolean Relations and the Incomplete Specification of
Logic Networks
R.K. Brayton and F. Somenzi
231
6.3.
Designing ffigh-Performance Digital Circuits Using
Wave Pipelining
D. Wong, G.
De Micheli,
and
M. Flynn
241
Session
7:
Language and Co-Processors
7.1.
VLSI Packaging Technologies for High Speed Electronic Systems
T. Ohsaki
255
7.2.
Design and Fabrication of Pegasus Prolog Processor
K.
Seo
and Y. Yokota
265
7.3.
A VLSI Coprocessor Implementing the Programming
Language Scheme
J. Lohse and R.
Rauscher 275
7.4.
Implementation of LSI Sort Chip for Bimodal Sort Memory
M. Kitsuregawa, W. Yang, S. Fushimi, H. Kimura, J. Shinano,
and Y. Kasahara
285
7.5.
PIPE: a Hardware Accelerator for
Scanline
Interpolation and
Hidden Surface Removal
K.S. Eo, CM. Kyung, and
S.S.
Kim
295
Contents
Session 8:
Memories and
Special
Architectures
8.1.
ASIC Intelligent Memory (Invited)
T. Iizuka
307
8.2.
The Design of a Content Associative Memory
Wu Hongjiang and Qiu Yulin
319
8.3.
Functional Memory Type Parallel Architecture for
Image Processing
A.
Nakano,
H.
Yasuura, and
K. Tamaru
329
8.4.
WSI
Array Processors with
Reconfigurable
Links
Yi-Chieh Chang and K.G. Shin
339
8.5.
Bit-Serial Pre-Processing for Recognition of Hand-Written
Drawing Image Using CMOS Neural Module
H. Takakubo and K. Shono
349
Session
9:
Signal Processing
9.1.
An Illustration of
Micropipelines
Using Two-Dimensional
Fourier Transform Architectures
J.C. Mudge
359
9.2. 20
MHZ
16
x
16
Discrete Cosine Transform
1С:
CAD and
Architectural Methodology
S.G. Smith and J.M. Rischard
369
9.3.
A Comparison of Path Memory Techniques for
VLSI Viterbi Decoders
DJ. Coggins, DJ.
Skellern, R.A. Keaney, and JJ. Nicolas
379
9.4.
MIMIC, A Custom VLSI Parallel Processor for
Musical Sound Synthesis
J. Wawrzynek and T.
von Eicken 389
Session
10:
Routing
10.1.
Global Routing in a Module Generation Environment
I. Vandeweerd, P. Six, and H.
De Man 401
10.2.
Mercury: A New Approach to Macro-Cell Global Routing
Y. Nishizaki, M. Igusa, and A. Sangiovanni-Vicentelli
411
Contents
Session 11:
Placement
11.1. Macrocell
Placement
by
Global
Optimization with
Uniform Cell Distribution
H.Ch.
Ranke
and F.M. Johannes
423
11.2.
Process-Independent
ŽD-Compaction
in a Symbolic Design
Environment
W. Bonath and M. Glesner
433
11.3.
Sea-of-Gates Placement by Simultaneous Quadratic
Programming Combined with Improved Partitioning
J.M. Kleinhans,
G.
Sigi,
and F.M. Johannes
445
11.4.
Fang: A Joiner for Compacted Cells
С
Cheng and A.M. Despain
455
11.5.
Flexible Boundaries for Layout Synthesis
M. Lefebvre and Chong Chan
465
Session
12:
Closing Session
12.1.
Analytically Based Yield Simulation of VLSI Macrocells
I. Chen and
AJ.
Strojwas
477
12.2.
Microdynamic Structures on Silicon
R.S.
Muller
487
Appendix
Special Session: Framework
A.I. An Object-Oriented Modular Approach to Design Management
M.
Treffers,
P. van
den Hamer,
M.
Cariili, C. Fasce,
P. Gubian,
F. Bretschneider,
A. Hsu,
and H.
Lagger 497
A.2. The NMP-CADLAB Framework
J.
Haabma,
В.
Steinmüller,
P.-A.
Gussander, and
T. Lengauer
505
Author
Index
515 |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV004441853 |
| callnumber-first | T - Technology |
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| classification_rvk | SS 1989 |
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| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| spelling | VLSI 89 proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 ed. by G. Musgrave ... Amsterdam u.a. North-Holland 1990 XIII, 516 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Circuits intégrés à très grande échelle - Congrès Circuits intégrés à très grande échelle - Congrès ram VLSI inriac architecture VLSI inriac architecture dédiée inriac architecture processeur inriac conception VLSI inriac coprocesseur inriac optimisation inriac processeur VLSI inriac simulation inriac synthèse VLSI inriac test VLSI inriac traitement signal inriac vérification inriac Integrated circuits Very large scale integration Congresses Digitaltechnik (DE-588)4012303-0 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1989 München gnd-content VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s DE-604 Digitaltechnik (DE-588)4012303-0 s Musgrave, G. Sonstige oth International Conference on Very Large Scale Integration 5 1989 München Sonstige (DE-588)5045228-9 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002755615&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | VLSI 89 proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 Circuits intégrés à très grande échelle - Congrès Circuits intégrés à très grande échelle - Congrès ram VLSI inriac architecture VLSI inriac architecture dédiée inriac architecture processeur inriac conception VLSI inriac coprocesseur inriac optimisation inriac processeur VLSI inriac simulation inriac synthèse VLSI inriac test VLSI inriac traitement signal inriac vérification inriac Integrated circuits Very large scale integration Congresses Digitaltechnik (DE-588)4012303-0 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4012303-0 (DE-588)4121208-3 (DE-588)4117388-0 (DE-588)1071861417 |
| title | VLSI 89 proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 |
| title_auth | VLSI 89 proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 |
| title_exact_search | VLSI 89 proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 |
| title_full | VLSI 89 proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 ed. by G. Musgrave ... |
| title_fullStr | VLSI 89 proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 ed. by G. Musgrave ... |
| title_full_unstemmed | VLSI 89 proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 ed. by G. Musgrave ... |
| title_short | VLSI 89 |
| title_sort | vlsi 89 proceedings of the ifip tc 10 wg 10 5 international conference on very large scale integration munich federal republic of germany 16 18 august 1989 |
| title_sub | proceedings of the IFIP TC 10 WG 10.5 International Conference on Very Large Scale Integration Munich, Federal Republic of Germany, 16 - 18 August, 1989 |
| topic | Circuits intégrés à très grande échelle - Congrès Circuits intégrés à très grande échelle - Congrès ram VLSI inriac architecture VLSI inriac architecture dédiée inriac architecture processeur inriac conception VLSI inriac coprocesseur inriac optimisation inriac processeur VLSI inriac simulation inriac synthèse VLSI inriac test VLSI inriac traitement signal inriac vérification inriac Integrated circuits Very large scale integration Congresses Digitaltechnik (DE-588)4012303-0 gnd Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Circuits intégrés à très grande échelle - Congrès VLSI architecture VLSI architecture dédiée architecture processeur conception VLSI coprocesseur optimisation processeur VLSI simulation synthèse VLSI test VLSI traitement signal vérification Integrated circuits Very large scale integration Congresses Digitaltechnik Entwurf Konferenzschrift 1989 München |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002755615&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT musgraveg vlsi89proceedingsoftheifiptc10wg105internationalconferenceonverylargescaleintegrationmunichfederalrepublicofgermany1618august1989 AT internationalconferenceonverylargescaleintegrationmunchen vlsi89proceedingsoftheifiptc10wg105internationalconferenceonverylargescaleintegrationmunichfederalrepublicofgermany1618august1989 |