1990 proceedings: January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Washington u.a.
IEEE Computer Society Pr.
1990
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIV, 341 S. Ill., graph. Darst. |
| ISBN: | 0818690135 0818660139 |
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| 111 | 2 | |a International Conference on Wafer Scale Integration |n 2 |d 1990 |c San Francisco, Calif. |j Verfasser |0 (DE-588)5045424-9 |4 aut | |
| 245 | 1 | 0 | |a 1990 proceedings |b January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA |c International Conference on Wafer Scale Integration. Ed. by Joe Brewer ... |
| 264 | 1 | |a Washington u.a. |b IEEE Computer Society Pr. |c 1990 | |
| 300 | |a XIV, 341 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 7 | |a ARCHITECTURE (COMPUTERS) |2 nasat | |
| 650 | 7 | |a CHIPS (MEMORY DEVICES) |2 nasat | |
| 650 | 7 | |a CONFERENCES |2 nasat | |
| 650 | 7 | |a Circuits intégrés - Congrès |2 ram | |
| 650 | 4 | |a Circuits intégrés - Intégration sur la plaquette - Congrès | |
| 650 | 7 | |a FAULT TOLERANCE |2 nasat | |
| 650 | 7 | |a INTEGRATED CIRCUITS |2 nasat | |
| 650 | 7 | |a LARGE SCALE INTEGRATION |2 nasat | |
| 650 | 7 | |a MICROELECTRONICS |2 nasat | |
| 650 | 7 | |a PRODUCT DEVELOPMENT |2 nasat | |
| 650 | 7 | |a WAFERS |2 nasat | |
| 650 | 7 | |a WSI |2 inriac | |
| 650 | 7 | |a architecture WSI |2 inriac | |
| 650 | 7 | |a conception WSI |2 inriac | |
| 650 | 7 | |a technologie WSI |2 inriac | |
| 650 | 7 | |a test WSI |2 inriac | |
| 650 | 7 | |a tolérance panne |2 inriac | |
| 650 | 4 | |a Integrated circuits |x Wafer-scale integration |v Congresses | |
| 650 | 0 | 7 | |a Wafer-Integration |0 (DE-588)4226609-9 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1990 |z San Francisco Calif. |2 gnd-content | |
| 689 | 0 | 0 | |a Wafer-Integration |0 (DE-588)4226609-9 |D s |
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-002734966 | ||
Datensatz im Suchindex
| _version_ | 1804118584855625728 |
|---|---|
| adam_text | Table of Contents
General Chair s Message
.....................................
v
Program Chair s Message
....................................
vii
Conference Committee
......................................ix
Plenary Session
Wafer Scale Integration
-
ТЪе
Vision
..............................1
E
A. Sack
WSI
Perspectives and Projections
................................3
ľ.
Hsia and W. Geideman
Sessioni:
WSI
Devices
Chair: VK.Jain
A 200-Mb Wafer Scale Memory
.................................5
F.
Baba
and A. Sinclair
Progress in
WSI SRAM
Development
.............................13
R. Bourassa, T. Coffman, andJ-E. Brewer
The Lincoln Programmable Image-Processing Wafer
....................20
R.
Berger,
A. Bertapelli, R.
Frankéi,
J J.
Hunt,
J.
Mann,
J J.
Raffel, FM.
Rhodes,
A.
Soares,
and C. Woodward
MUSE: A Wafer-Scale Systolic DSP
.............................27
Dl,. Allen, AM. Anderson, CM. Radar, and C. Woodward
WASP: A Wafer-Scale Massively Parallel Processor
....................36
RM.
Lea
The WASP Demonstrator Programme: the Engineering of a Wafer-Scale System
... 43
IJř.
Jalomecki and SJ. Hedge
RF-Wafer Scale Integration: A New Approach
ω
Active Phased Arrays
........50
LJR. Whicker, JJ.
Zingaro,
M.C.
Driver, and
R.C.
Clarke
A
64Mb
MROM With Good Pair Selection Architecture
..................57
N.
Nakahara, H. Hatanaka,
S. Kura,
Y. Suminaga,
Y. Hotta, M. Okada, and K. Miyata
A
High
Performance Single Chip FFT
Array Processor
for
WSI
..............60
J.
You and
SS.
Wong
Implementation of Configurable Hardware Using Wafer Scale Integration
.......68
T. Kean, J. Gray, andB. Pruniaux
Session 2:
WSI
Architecture
Chair:
RM.
Lea
Crosspoint Arithmetic Processor Architecture for Wafer Scale Integration
........75
J.T.
Arcos,
В.
Evans, and S.Y.
Kung
A linear-Array
WSI
Architecture for Improved Yield and Performance
.........85
R.W. Horst
Introduction of a New Architecture for Wafer Integration
Through Configuration Hierarchies
.............................. 92
P. Nunalty
WSI
Architecture for L-U Decomposition: A Radar Array Processor
..........102
VJĹ.
Jain and
DL. Landis
Defect Tolerance Scheme for GigaFLOP
WSI
Architectures
...............109
A3.
Singh and H.Y.Youn
A General Configurable Architecture for
WSI
Implementation
f
or Neural Nets
. . . .116
F.
Distante,
M.G.
Sami, and GS. Gajani
WSI
Architecture of
a Neurocomputer
Module
.......................124
U. Ramacher, M. Wesseling, andK. Goser
Defect Tolerant Sorting
Networks for WSI
Implementation
................131
S.-C.
Liang andS.-Y.
Kuo
Data Manipulator
Network for
WSI
Designs
........................138
JM.
Wills and
VX.
Jain
Session
3:
WSI FauH
and Defect Tolerance
Chair:
W
X.
Fuchs
Multiple Fault Detection and Location in
WSI
Baseline
Interconnection Networks
...................................145
С
Feng, W.-K. Huang, andF.
Lombardi
Effects of Switch Failure on Soft-Configurable
WSI
Yield
................152
M.
Blatt
Defect Tolerant Implementations for Feed-Forward and
Recurrent Neural Networks
...................................160
P. Franzon, D. Van den Bout, J.
Paulos,
Ί.
Miller,
III, W. Sny
der,
T.
Nagle,
and W. Liu
A Visually Oriented Architectural Fault Simulation Environment for
WSI
.......167
P.
G.
Ryan, D.G. Saab, and WK.
Fuchs
Hierarchical Fault Tolerance for
3D
Microelectronics
...................174
M. Campbell, M. Little, and M. Yung
Distributed
Diagnosis
for Wafer-Scale Systems
.......................189
Y.-H. Choi
Fault Tolerance Performance of
WSI
Systolic Sorter
....................196
S. Horiguchi
Fault-Tolerant
WSI
Array Processors: the Use of
Berger
Codes in Parallel Arithmetic-Logic Units
..................... 203
V. Pluri
Session
4:
WSI
DesigrVTest Strategies
Chair: P. Wyatt
A Defect and Fault Tolerant Design of
WSI
Static RAM Modules
...........213
N.Tsuda
A Methodology for Wafer Scale Integration of Linear Pipelined Arrays
........220
R. Ramaswamy, G. Brebner, andD. Aspinall
Some New Algorithms for Reconfiguring VLSI/WSI Arrays
...............229
T. Varvarigou,
VJř.
Roychowdhury, and T. Kailath
Bypass Switch Design for Defect-Tolerant Arrays
.....................236
D
МЛ.
Walker
Yield Enhancement for
WSI
Array Processors Using
Two-and-Half-Track Switches
................................243
J.SN.
Jean, H.C. Fu,
and S.Y.
Kung
Testing Wafer-Scale Arrays: Constant Testability Under Multiple Faults
.......251
D. Sciuto andF.
Lombardi
A Self-Test Methodology for Restracturable
WSI
.....................258
Dl,. Landis
Divide and Conquer in Wafer-Scale Array Testing
.....................265
Y.-H. Choi and T.Jung
Session
5:
WSI
Design and Support Technology
Chair: JF. McDonald
Yield Modeling and Optimization of Large Redundant RAMs
..............273
K.
N.
Ganapathy,
ÅH.
Singh, andDX. Pradhan
Power Distribution Strategies Based on Current Estimation and Simulation of
Lossy
Transmisáon
Lines in Conjunction with Power Isolation Circuits
........288
U. Jagau, K.-P. Dyck, H. Grabinski,
HJ.
Iden,
and M. Kuboschek
Investigations of Nd: YAG Laser Formed Connections and
Disconnections of Standard CMOS Double Level Metallizations
............298
H.-D.
Hartmann
and T. Hilhnann-Ruge
Hybrid
Wafer Scale Interconnection Inventing a New Technology
...........308
R. Schmidt
WSI
Implemented with Button Board Interconnection
...................317
J.T.
Arcos,
W.
T.
Kamiyama,
E.E. Swartzlander, and W.K. Young
A Study of High Density Multilayer LSI
...........................322
M. Matsunami, M.
Roba,
and
R.
Miyake
WaferScalelntegrationof Programmable Gate Arrays
..................329
J ľ.
McDonald,
S. Dohral,
R. Phtlhower, andME. Russinovich
SuperChip
Packaging Issues
..................................339
P. Ritlop
Auttior Index
...........................................341
|
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| genre | (DE-588)1071861417 Konferenzschrift 1990 San Francisco Calif. gnd-content |
| genre_facet | Konferenzschrift 1990 San Francisco Calif. |
| id | DE-604.BV004407288 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:12:38Z |
| institution | BVB |
| institution_GND | (DE-588)5045424-9 |
| isbn | 0818690135 0818660139 |
| language | English |
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| spelling | International Conference on Wafer Scale Integration 2 1990 San Francisco, Calif. Verfasser (DE-588)5045424-9 aut 1990 proceedings January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA International Conference on Wafer Scale Integration. Ed. by Joe Brewer ... Washington u.a. IEEE Computer Society Pr. 1990 XIV, 341 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier ARCHITECTURE (COMPUTERS) nasat CHIPS (MEMORY DEVICES) nasat CONFERENCES nasat Circuits intégrés - Congrès ram Circuits intégrés - Intégration sur la plaquette - Congrès FAULT TOLERANCE nasat INTEGRATED CIRCUITS nasat LARGE SCALE INTEGRATION nasat MICROELECTRONICS nasat PRODUCT DEVELOPMENT nasat WAFERS nasat WSI inriac architecture WSI inriac conception WSI inriac technologie WSI inriac test WSI inriac tolérance panne inriac Integrated circuits Wafer-scale integration Congresses Wafer-Integration (DE-588)4226609-9 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1990 San Francisco Calif. gnd-content Wafer-Integration (DE-588)4226609-9 s DE-604 Brewer, Joe Sonstige oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002734966&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | 1990 proceedings January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA ARCHITECTURE (COMPUTERS) nasat CHIPS (MEMORY DEVICES) nasat CONFERENCES nasat Circuits intégrés - Congrès ram Circuits intégrés - Intégration sur la plaquette - Congrès FAULT TOLERANCE nasat INTEGRATED CIRCUITS nasat LARGE SCALE INTEGRATION nasat MICROELECTRONICS nasat PRODUCT DEVELOPMENT nasat WAFERS nasat WSI inriac architecture WSI inriac conception WSI inriac technologie WSI inriac test WSI inriac tolérance panne inriac Integrated circuits Wafer-scale integration Congresses Wafer-Integration (DE-588)4226609-9 gnd |
| subject_GND | (DE-588)4226609-9 (DE-588)1071861417 |
| title | 1990 proceedings January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA |
| title_auth | 1990 proceedings January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA |
| title_exact_search | 1990 proceedings January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA |
| title_full | 1990 proceedings January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA International Conference on Wafer Scale Integration. Ed. by Joe Brewer ... |
| title_fullStr | 1990 proceedings January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA International Conference on Wafer Scale Integration. Ed. by Joe Brewer ... |
| title_full_unstemmed | 1990 proceedings January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA International Conference on Wafer Scale Integration. Ed. by Joe Brewer ... |
| title_short | 1990 proceedings |
| title_sort | 1990 proceedings january 23 25 1990 fairmont hotel san francisco california usa |
| title_sub | January 23 - 25, 1990 Fairmont Hotel, San Francisco, California, USA |
| topic | ARCHITECTURE (COMPUTERS) nasat CHIPS (MEMORY DEVICES) nasat CONFERENCES nasat Circuits intégrés - Congrès ram Circuits intégrés - Intégration sur la plaquette - Congrès FAULT TOLERANCE nasat INTEGRATED CIRCUITS nasat LARGE SCALE INTEGRATION nasat MICROELECTRONICS nasat PRODUCT DEVELOPMENT nasat WAFERS nasat WSI inriac architecture WSI inriac conception WSI inriac technologie WSI inriac test WSI inriac tolérance panne inriac Integrated circuits Wafer-scale integration Congresses Wafer-Integration (DE-588)4226609-9 gnd |
| topic_facet | ARCHITECTURE (COMPUTERS) CHIPS (MEMORY DEVICES) CONFERENCES Circuits intégrés - Congrès Circuits intégrés - Intégration sur la plaquette - Congrès FAULT TOLERANCE INTEGRATED CIRCUITS LARGE SCALE INTEGRATION MICROELECTRONICS PRODUCT DEVELOPMENT WAFERS WSI architecture WSI conception WSI technologie WSI test WSI tolérance panne Integrated circuits Wafer-scale integration Congresses Wafer-Integration Konferenzschrift 1990 San Francisco Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002734966&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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