Proceedings of the IEEE 1990 Custom Integrated Circuits Conference: The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990
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| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Institute of Electrical and Electronics Engineers
1990
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | Getr. Zählung zahlr. Ill. u. graph. Darst. |
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| 245 | 1 | 0 | |a Proceedings of the IEEE 1990 Custom Integrated Circuits Conference |b The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 |
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Datensatz im Suchindex
| _version_ | 1804118583883595776 |
|---|---|
| adam_text | CONTENTS
SESSION
1
SUNDAY EVENING
___________________________
America South Ballroom
7:00
NEW PRODUCTS—NEW DIRECTIONS
Chairman: A. Silzars
SESSION
2
SUNDAY EVENING
_________________________
Essex Center/South Ballroom
7:00
NEW PRODUCTS—NEW HARDWARE
&
SOFTWARE TOOLS
Chairman: H.Scaif
SESSION
3
SUNDAY EVENING
________________________
America Center Ballroom
7:00
NEW PRODUCTS—NEW HARDWARE PRODUCTS
Chairman: M. Pope
SESSION
4
MONDAY MORNING
__________________________
America South Ballroom
_______________
PAPER
#
8:00
WELCOME/OPENING REMARKS
M. Hartranft, General Chairman
D, Brown, Conference Chairman
8:20
CICC
90—
TECHNICAL PROGRAM
J. Lipman, Technical Program Committee Chairman
8:30
KEYNOTE ADDRESS
ASIC Technological Developiment of the 90 s and Beyond: Evolution or Revolution?
L. Roffelsen,
VP
of ASIC Operations, Fujitsu Microelectronics, Inc.
9:30
HIGH DENSITY/PERFORMANCE GATE ARRAYS
Chairman: R. Blake
Co-Chairman: G. Sporzynski
9:35
High Performance CMOS Array with an Embedded Test Structure
4.1
K. Pierce and R. Lipp,
Cross-Check
Technology, Inc., San Jose, CA; E. Chan and T. Wong, LSI Logic Corp.,
Milpitas, CA
10:00
A Bipolar-PMOS Merged Basic Cell for
0.8
Micron BiCMOS Sea-of-Gates
4.2
T. Hanibuchi, M. Ueda, K. Higashitani, M. Hatanaka and K. Mashiko, Mitsubishi Electric Corp., Hyogo, Japan
10:25
A
150
К
Gate 250ps BiCMOS
SOG
with an Emitter-Foiiowered CMOS (ECMOS)
Celi
4.3
К.
Kumagai,
К.
Yoshida,
T.
Hatano,
H.
Masuda,
H.
Nakazało,
Y.
Tagami
and H.
Mizumura, NEC Corp., Kawasaki,
Japan
A
35,000
Gate Mixed ECL BiCM^i
ţ|e
Array
D.S.
Rosky and L.T.
Lin. ¿&átr ^F^L.aiits
Corp., San Diego, CA
tx
CONTENTS
10:50
A
30,000 Gate ECL Gate
Array Using
Advanced Single
Poly
Technology
and Four
Level
Metal
4.4
Interconnect
G.
Ganschow,
L.
Yee,
L.
Ho,
M.
Truong,
F. Haas, S.P. Joshi, P. Smith, R.
Jerome,
R. Lahri, L.
Bouknight,
M.
Biswal
and
N.
Lam, National
Semiconductor Corp., Puyallup, WA
11:15
A 20K Ga
As Array wit
h
1
0K
of Embedded
SR
AM
4.5
R.
Hinds,
S.
Canaga,
G.
Lee and A. Choudhury, Vitesse Semiconductor Corp., Camarillo,
CA
11
:40 LATE NEWS PAPER
4.6
А гбОК-Сігсиії
ASIC Family Using a DRAM Technology
M.D. Weir,
J.E. Kita,
T.J. Cockerill, P.F.
Hynek,
T.M. Lepsic,
Т.К.
Та, В.К.
Wong, S.R. Woodham and R.R. Young,
IBM General Technology Division, Essex Junction, VT
SESSION
5
MONDAY MORNING
__________________________
Essex Center/South Ballroom
_______________
PAPER
#
9:30
MIXED-LEVEL SIMULATION
&
BEHAVIORAL MODELING
Chairman: B.Sheu
Co-Chairman: V. Rao
9:35
A New Approach to Event-Driven Analog/Digital Simulation
5.1
T. Vucurevich, Analog Devices, Wilmington, MA
10:00
IDSIM2: An Environment for Mixed-Mode Simulation
5.2
D. Overhauser, Duke University, Durham, NC;and I. Hajj, University of Illinois,
Urbana,
IL
10:25
ROOMMS—A Relaxation-based, Object-Oriented, Mixed-Mode Simulator
5.3
J.A. Watts andT.A.
Kwasniewski, Carleton
University, Ottawa, Ontario, Canada
10:50
Development of an Analog Hardware Description Language
5.4
CM. Kurker and J. J.
Paulos,
North Carolina State University, Raleigh, NC; and B.S. Cohen and E.S. Cooley,
Dartmouth College, Hanover, NH
11:15
Behavioral Analog Circuit Models for Multiple Simulation Environments
5.5
L.
Moser,
IBM Corp., San Jose, CA
11
:40 A Sophisticated CPU Simulation
Usine
ÍMt4řioral
Language Models
5.6
D.N. Krening, J.M. Roucis,
P
A.fiťyaQ^ř^^.aiietta
Space Systems, Denver, CO
12:05
LATE NEWS PAPER ™
5.7
A Behavior Model of A/D Converters Using a Mixed-Mode Simulator
G. Ruan, Analogy, Inc., Beaverton, OR
CONTENTS
SESSION
6
MONDAY MORNING
_________________________
America Center Ballroom
_______________
PAPER
#
9:30
DATA CONVERTERS
Chairman: I. Scott
Co-Chairman:
A. Grebene
9:35
Fact Successive-Approximation A/D Converters
6.1
K. Hadidi and G.C. Temes, University of California, Los Angeles, CA; V.S. Tso, Sierra Semiconductor, San Jose,
CA
10:00
A Self-Calibrating 16Bit
6 ms
CMOS Audio ADC
6.2
J. Gotoh, T. Satoh and
T. lida,
Toshiba Semiconductor System
Eng.
Ctr., Kawasaki, Japan; and H. Kishigami,
Toshiba Micro-Electronics Ctr.
,
Kawasaki
,
Japan
10:25
A First-Order Current-Steering
Sigma-Delta
Modulator
6.3
V.
Comino
and G.C. Temes, University of California, Los Angeles, CA; and M. Steyaert,
Katholieke
University,
Leuven,
Belgium
10:50
An 8b
50
MHz 225mW
Submicron
CMOS ADC Using Saturation Eliminated Compactors
6.4
T. Matsuuraand H.
Kojima,
Hitachi, Ltd., Tokyo, Japan; E. Imaizumi and K.
Usui,
Hitachi VLSI
Eng.
Corp., Tokyo,
Japan; and S. Ueda, Hitachi, Ltd., Gunma, Japan
11:15
A
7
Channel
Levei
Generator
Chipfora
VLSI Digital Tester
6.5
G. Sheehan, Analog Devices, Wilmington, MA; G. McGlinchey, Analog Devices, Dublin, Ireland; and K. Wilsher,
Schlumberger Technologies, San Jose, CA
11:40
A High Speed
EEPROM
Configurable Digital to Analog Converter Array
6.6
D. Oto
and K. Venkateswaran, Avasem Corp., San Jose, CA; and R. Habitzreiter, Recognition Equipment, Inc.,
Dallas,
TX
12:05
LATE NEWS PAPER
6.7
Low-Cost CMOS Digital-Analogue
Convertor
for Video Applications
J.E. Franca and J.C. Vital, Inst. Superior
Tecnico,
Lisboa,
Portugal
SESSION?
MONDAY MORNING
__________________________
Essex North Ballroom
________________
PAPER
#
9:30
INTEGRATED SENSORS AND PROCESSORS
Chairman: L. D Luna
Co-Chairman: M. Hartranft
9:35
Integrated Sensor and Rangefinding Analog Signal Processor
7.1
L.R. Carley, A. Gruss and T.
Kanade,
Carnegie Mellon University, Pittsburgh, PA
10:00
An Active Thin-Film Magnetic Head with
60
MHz Bandwidth and Internal Amplification of
58 dB 7.2
H.
Rudolph, FhG
Arbeitsgruppe
fur
Integrierte Schaltungen, Erlangen,
W. Germany;
К.
Vernie
and D.
Seitzer,
Univ. Erlangen-Nurnberg,
Erlangen, W.
Germany
10:25
ASIC
Vision
7.3
D.
Renshaw,
P. Denyer,
G. Wang
and
M. Lu,
University of Edinburgh, Edinburgh, U.K.
10:50
Design of a
64
x
64
Photo Current Multiplexer for Use in Astronomical Applications
7.4
C. Steele and C.F. Walmsley, Walmsiey (Microelectronics) Ltd., Edinburgh, Scotland; A. Timlin and M. Salcido,
Cincinnati Electronics Corp., Mason, OH
11:15
A Digital Signal Processor for Linear Sensors
7.5
W.A. Cook, K.A. Parulski, L. J. D Luna, G. W. Brown and R.M. Guidash, Eastman Kodak Co., Rochester, NY
xi
CONTENTS
11:40
Time Integrating Correlator (TIC) for
Real-Time
Processing of Spread-Spectrum Signals
7.6
D. Beeler and H.
Kaufmann,
Ascom Zelcom
AG, Hombrechtikon,
Switzerland
12:05
LATE NEWS PAPER
7.7
ALPHA, A New Contact Type Linear Image Sensor
H. Goto, K. Maemura and K. Morimune, Toshiba Corp., Kawasaki, Japan; and T.
Tada
and T. Sato, Toshiba Micro¬
electronics Corp., Kawasaki, Japan
SESSION
8
MONDAY AFTERNOON
_________________________
America South Ballroom
_________________
PAPER
#
2:00
ANALOG DESIGN TECHNIQUES
Chairman: D. Wayne
Co-Chairman:
A. Grebene
2:05
Design Considerations for CMOS Switched-Current Filters
8.1
DJ. Allstot,
T.S.
Fiez
and G. Liang, Oregon State University, Corvallis, OR
2:30
A 1.4V Switched Capacitor Filter
8.2
T. Adachi, A. Ishikawa, A. Barlow and K. Takasuka, Asahi Kasei Microsystems, Tokyo, Japan
2:55
A High Frequency Fully Differential BiCMOS Operational Amplifier
8.3
A.N.
Karanicolas, K.K. O, J.Y. Wang, H.S. Lee and R.L.
Reif, MIT,
Cambridge, MA
3:20
A High-Speed CMOS Amplifier with Dynamic Frequency Compensation
8.4
B.W.
Lee and B.J. Sheu, University of Southern California, Los Angeles, CA
3:45
Rapid Yield Estimation as a Computer Aid for Analog Cell Design
8.5
T. Mukherjee and L.R. Carley, Carnegie Mellon University, Pittsburgh, PA
4:10
LATE NEWS PAPER
8.6
An intelligent Analog Design System Based on Manipulation of Design Equations
K. Swings, G. Gielen and W.
Sansen,
Katholieke Univ. Leuven, Leuven,
Belgium
4:25
LATE NEWS PAPER
8.7
Pole-Zero Simualtor with Component Sensitivity Analysis Function
T. Eton, NEC Corp., Kanagawa, Japan
4:40
LATE NEWS PAPER
8.8
An Accurate and Compact Model for the Transient Simulation of Continuous-Time Filters
R. Trihy and
C. Lyden,
National Microelectronics Research Center, Cork, Ireland
XII
CONTENTS
SESSION
9
MONDAY AFTERNOON
_______________________
Essex Center/South Ballroom
_______________
PAPER
#
2:00
LOGIC SIMULATION
&
DELAY ESTIMATION
Chairman: B. Sheu
Co-Chairman: R.
Milano
2:05
Logic Simulation Using a Message-Driven Approach on MIMD Computers
9.1
S. Shimogori and T. Kage, Fujitsu Laboratories Ltd., Kawasaki,Japan
2:30
Mixed Behavior-Logic Simulation in a Hardware Accelerator
9.2
P. Agrawai, AT&T Bell Labs., Murray Hill, NJ
2:55
IDEAS: A Delay Estimator and Transistor Sizing Tool for CMOS Circuits
9.3
S.S.
Sapatnekar and V.B. Rao, University of Illinois,
Urbana,
IL
3:20
A New Circuit Recognition
&
Reduction Method for Pattern Based Circuit Simulation
9.4
G. Yokomizo,
С
Yoshida, M. Miyamaand Y. Motono, Hitachi, Ltd., Tokyo, Japan; and K. Nakajo, Hitachi VLSI
Eng.
Corp.
3:45
CHARMS: Characterization and Modeling System for Accurate Delay Prediction of ASIC
9.5
Designs
D.
Patel,
LSI Logic Corp., Milpitas, CA
4:10
Efficient On-Chip Delay Estimation for Leaky Models of Multiple-Source Nets
9.6
P.R. O Brien andT.L. Savarino, Cadence Design Systems, Inc., Santa Clara, CA
SESSION
10
MONDAY AFTERNOON
______________________
America Center Ballroom
_______________
PAPER
#
2:00
DESIGN: MYTHS, METHODS
&
SYSTEMS
Chairman:
T. Sideris
Co-Chairman: R. Bryant
2:05
VLSI Design Theory: Tenacious Myths and Economic Constraints
10.1
K.
Klingsheim
and O. Aaserud, University of
Trondheim, Trondheim,
Norway
2:30
Fundamentals of Design Management Systems Development
10.2
M.
Zanella
and P. Gubian,
Universita
degli Studi di
Brescia, Brescia, Italy
2:55
A Mixed Level Simulator Mega-FAL with Novel Data Structure Oriented to HDL Statements
10.3
M. Aihara and M. Sekine, Toshiba Corp., Kawasaki, Japan
3:20
А ЗООК-Сігсиії
ASIC Logic Family CAD System
10.4
J.H. Panner, R.P.
Abato,
R.W.
Bassett,
K.M.
Carrig,
P.S.
Gillis,
DJ. Hathaway and T.W. Sehr, IBM Corp.,
Essex Junction,
VT
3:45
A
Technical
Strategy for Mixed Analog-Digital Customs
10.5
RJ.
Brewer, Analog Devices, Newbury, England
4:10
A Knowledge Based Simulation Environment
10.6
K. Miizner, Univ. of Dortmund, Dortmund, W. Germany; and
F. Krohm, Fraunhofer
Institute of Microelectronic
Circuits
&
Systems,
Duisburg, W.
Germany
4:35
LATE NEWS PAPER
10.7
Towards Computer Aided Specification of Analog Components
J. Bortolazzi and K.D. Mueller-Glaser, University of
Erlangen-Nuemberg, Erlangen, W.
Germany
ХШ
CONTENTS
SESSION
11
MONDAY AFTERNOON
__________________
Essex North Ballroom
_________________
PAPER
#
2:00
INTERFACE CIRCUITS
&
INTERCONNECTS
Chairman: W.Vincent
Co-Chairman: J.
Tandon
2:05
High Density Central I/O Circuits for CMOS
11.1
R.P.
Masleid,
IBM Corp., Austin,
TX
2:30
Crosstalk Analysis of High-Speed Interconnects and Packages
11.2
H. You and M.
Soma,
University of Washington, Seattle, WA
2:55
Effect of Device and Interconnect Scaling on the Performance and Noise of Packaged CMOS
11.3
Devices
R. Senthinathan and J.L. Prince, University of Arizona, Tucson, AZ
3:20
A Full
1.2
Micron CMOS ECL-CMOS-ECL
Convertor
with Subnanosecond Settling Times
11.4
M. Steyaert,
Katholieke
Univ.
Leuven, Leuven,
Belgium;
W.
Bijker and P. Vorenkamp, Univ. Twente,
Enschede,
Netherlands; and J. Sevenhans, Alcatel, Antwerp, Belgium
3:45
A High Performance, Low Noisp
■.•^ţţvwer,
Backplane Driver Using
0.7
Micron HCMOS
11.5
Technology
MltYţD^
T.
Nguyen and T. Wong,
Tţ.Vogic
Corp., Milpitas, CA
4:10
CMOS Amplifiers Incorporating a Novel Slew Rate Enhancement Technique
11.6
K. Nagaraj, AT&T Bell Labs., Murray Hill,
N J
4
:35 LATE NEWS PAPER
11.7
Current Control Buffer for
Multi
Switching CMOS
SOG
I. Tomioka, M. Hyozo, M. Okabe, S. Kishida, T. Arakawa and Y. Kuramitsu, Mitsubishi Electric Corp., Hyogo, Japan
SESSION
12
TUESDAY MORNING
___________________________
America South Ballroom
_________________
PAPER
#
8:30
TELECOMMUNICATIONS CIRCUITS
&
SYSTEMS
Chairman: D.
Embree
Co-Chairman:
Н
-S.
Lee
8:35
ISDN
U
Transceiver Analog Front-End
12.1
N.
van Bavel, M. Rybicki, C. Greaves, B. Valentine and S. Jackson, Motorola, Inc., Austin,
TX
9:00
An Analog Front End for a 2B1
Q
?<±
>»
к
^J
ţ^System
for the Digital Subscriber Link
12.2
J.
DeHaas,
Philips
Componer
ХјШ^Н*^ --^
л
Application
Lab.,
Eindhoven, The Netherlands
9:25
Integration of a CMOS Mixed-Analog-Digital Eight Channel Speech Transmission Circuit
12.3
F. Cepl, A. Deierling, O. Duffner, H.
Hauer
and D. Seitzer,
Fraunhofer Gesellschaft/Arbeitsgruppe
fur
Integrierte
Schaltungen, Erlangen, W.
Germany
9:50
A CMOS
Analog
Front-End Processor for an
FDM
System 12.4
K.R. Lakshmikumar,
L J.
Loporcaro and M.F. Tompsett, AT&T Bell Labs., Murray Hill, NJ; and J.C. Goetjen,
AT&T Bell Labs., Whippany, NJ
10:15
A Low-Power Low-Noise CMOS Compatible
80
V Subscriber Line Interface Circuit
12.5
E. Moons, E. Willcox, E. Op
de Beeck
and P.O. Guebels, Alcatel Bell Telephone Mfg. Co., Antwerp, Belgium
10:40
A BiCMOS Analog/Digital Array for Cellular Radio Applications
12.6
G.
Tröster,
P. Siebert, K. Schoppe, A.
Wedel,
E. Zocherand J.
Arndt, Telefunken
Electronic,
Heilbronn,
W. Germany;
T.
Becker
and
Н
-J.
Dressler,
AEG
Olympia, Ulm,
W. Germany;
G.
Bergmann,
Н
-J. Goiberg,
G.
Höppnerand
H.
Kling, AEG IC Research Center, Ulm,
W. Germany; W.
Schardein,
Α.
Rothermel and W. Esser,
Fraunhofer Institute, Duisberg,
W. Germany
11:05
A Sigma-Deità
Based Square-Law Compander
12.7
К.
Takasuka,
H.
Hisajima,
К.
Takahashi and A. Barlow, Asahi Kasei Microsystems, Tokyo, Japan
xiv
CONTENTS
SESSION
13
TUESDAY MORNING
_______________________
Essex Center/South Ballroom
_____________
PAPER
#
8:30
CODING
&
SIGNAL PROCESSING
Chairman: A. Roy
Co-Chairman: D. Brown
8:35
A Programmable
32
Tap Digital Interpolation Filter in
1.5
Micron CMOS with
80
MHz Output Data
13.1
Rate
W. Haberecht, E. DeMan and M.
Schulz,
Siemens
AG,
Munich, Germany
9:00
A
40
MHz Programmable and
Reconfigurable
Filter Processor
13.2
M.M.
Cai,
D.A. Luthi,
P.A.
Ruetzand P.H.
Ang,
LSI Logic Corp., Menlo Park, CA
9:25
A VLSI Grammar Processing Subsystem for a Real-Time Large Vocabulary Continuous-Speech
13.3
Recognition System
D.C. Chen, R. Yu, J. Rabaey and R.W. Brodersen, University of California, Berkeley, CA
9:50
A Complete Audio Decoder
1С
for U.S. Television Stereo Using Serial Arithmetic
13.4
C.B.
Dietrich, R.F. Nutter, R.J. Kolczynski and D.R. McClary, David Sarnoff Res. Ctr., Princeton, NJ;
T.J. Christopher,
G.G.
Tamer,
P.D.
Filliman andR.E. Morris, Thomson Consumer Elect., Indianapolis, IN
10:15
A 40-MHz Encoder-Decoder Chip Generated by a Reed-Solomon Code Compiler
13.5
P.
Tong,
LSI Logic Corp., Menlo Park, CA
10:40
A
25
MHz Viterbi FEC Codec
13.6
R. Kerr, H. Dehesh and D. Werner, Qualcomm, Inc., San Diego, CA; and A. Bar-David, IBM Corp., Israel
11
:05 An Opto-Electronic Viterbi Traceback Processor for Decoding Convolutional Codes
13.7
M.D. Alston and P. M. Chau, University of California, San Diego, CA
SESSION
14
TUESDAY MORNING
________________________
America Center Ballroom
_______________
PAPER
#
8:30
LOGIC
&
CIRCUIT SYNTHESIS I
Chairman: M. Mittal
Co-Chairman: J. Barnes
8:35
Timing Optimizations in a High Level Synthesis System
14.1
G. Gupta, D.
Pastorello
and G.D. House, SilcTechnologies, Inc.
9:00
Topology Decomposition for Area-Minimum Multi-Stage Complex Gates Synthesis
14.2
Z-J. Dai and K.
Asada,
The University of Tokyo, Tokyo, Japan
9:25
Real Area
-
Delay
-
Power Tradeoff in the EUCLID Logic Synthesis System
14.3
M.R.C.M.
Berkelaar
and
J.F.M. Theeuwen,
Eindhoven University of Technology, Eindhoven, The Netherlands
9:50
SAM: A Data Path Allocation System
14.4
N-S. Woo, AT&T Bell Labs., Murray Hill, NJ
10:15
New Design Approach for Configurable Data-Path
14.5
M. Shiochi, Y. Tanaka, M. Enkaku, T. Saigo and H. Suzuki, Toshiba
Соф.,
Kawasaki, Japan
10:40
FIRGEN: A CAD System for Automatic Layout Generation of High-Performance FIR Filters
14.6
R. Jain, P. Yang, B-Y. Chung, C.
Chien,
LK.Tan andT. Yoshino, University of California, Los Angeles, CA
11:05
LATE NEWS PAPER
14.7
Automatic Synthesis of Analog and Sample-Data Circuits in CMOS Technology
M. Negahban, Silicon Systems, Inc., Tustin, CA; and D. Gajski, University of California, Irvine, CA
11:20
LATE NEWS PAPER
14.8
Rule Based CAD Tool for Analog Circuit Synthesis and Layout Compilation
J. Trontelj, L. Tronteij, A. Pletersek and A. Vodopivec, University
Edvard Kardelj,
Ljubljana, Yugoslavia;
and G. Shenton, Graham Shenton Associates, Inc., Swindon, U.K.
xv
CONTENTS
11
:35
LATE
NEWS PAPER
14.9
MxSICO: A Mixed Analog Digital Compiler: Application to Oversampled A/D Converters
E. Berkcan, General Electric Co., Schnecteday, NY
SESSION
15
TUESDAY MORNING
__________________________
Essex North Ballroom
________________
PAPER
#
8:30
WIDGETS
Chairman: S. Chiao
Co-Chairman: D. Perkins
8:35
An Integrated
PLL
Clock Generator for
275
MHz Graphic Displays
15.1
G. Gutierrez, Brooktree Corp., San Diego, CA; and D.
DeSimone,
Quadic Systems Inc., Portland, ME
9:00
A ISMB/SBiCMOS Disk Drive Data Separator
15.2
V.
Condito,
Consultant, San Jose, CA; andC.H.
Lin, Exar
Corp., San Jose, CA
9:25
A CMOS VLSI Chess Microprocessor
15.3
J. Testa and A.M. Despain, University of California at Berkeley, Berkeley, CA
9:50
A Chip for Realtime Skeleting of images
15.4
R.
Rauscher
and A. Mader, University of Hamburg, Hamburg, W. Germany
10:15
A
66
MHz DSP Augmented
R
AMDAC for Smooth-Shaded Graphic Applications
15.5
S. Harston and R. Meaney, Analog Devices, Wilmington, MA;
N. Weste
and J. Leonard, TLW, Inc., North Andover,
MA; and L. Bodony, Edsun Labs. Inc., Waltham, MA
10:40
A Dynamically Tracking Clock Distribution Chip with Skew Control
15.6
D. Chengson, L. Costantino, A. Khan,
D. Le
and L. Yue, Tandem Computers Inc., Cupertino, CA
11
:05 A Hybridised, Multi-Channel, Charged Particle Detecting and Counting Array
15.7
J.V. Hatfield, T.A. York and P.J. Hicks, UMIST, Manchester, England; and J. Comer, University of Manchester,
Manchester, England
SESSION
16
TUESDAY AFTERNOON
______________________
America South Ballroom
_______________
PAPER
#
2:00
CELL BASED DESIGN
Chairman: K. Venkateswaran
Co-Chairman: Y. Horiba
2:05
SYMCELL: A Symbolic Standard Cell Design
16.1
K. Ramachandran and A.F. Kwan, Bellcore, Red Bank, NJ; R.R. Cordell, D.F. Daly and D.N.
Deutsch,
Bellcore,
Morristown, NJ
2:30
High Speed
0.55
Micron BiCMOS Family of ASICs
16.2
Y. Mehta, T. Wong and A. Tarn, LSI Logic Corp., Milpitas, CA
2:55
BUILDING-CELL Design Methodology for High-Speed GaAs Standard-Cell LSIs
16.3
T. Sasaki, K. Kawakyu, T. Seshita, A. Kameyama, T. Terada, Y.
Kitaura, N.
Uchitomi and
N.
Toyoda, Toshiba
Corp., Kawasaki, Japan
3:20
Clock Skew Reduction Approach for Standard Cell
16.4
T. Saigo, S. Watanabe, Y. Ichikawa, K. Mima and T. Yamamoto, Toshiba Corp., Kawasaki, Japan; S. Takayama
andT. Umetsu, Toshiba Microelectronics Corp., Kawasaki, Japan;and J. Santos and J. Buurma, Cadence
Design Systems, inc., San Jose, CA
3:45
A Flexible Multi-Port RAM Compiler for Datapath
16.5
H. Shinohara,
N.
Matsumoto, K. Fujimori and S.
Kato,
Mitsubishi Electric Corp., Hyogo, Japan
xvi
CONTENTS
4:10
A
High Performance One Micron CMOS Technology Chip 16.6
CG. Melrose and E.
Feng,
IBM Corp., San Jose, CA; and G. Klein, IBM Corp., Burlington, VT
4:35 An ADVANCELL® 1.0 Mainframe Chipset—2.2 Million Transistors
on
111Cs 16.7
L. Schrader and A. Weller, Siemens AG,
Munich,
W. Germany
SESSION 17
TUESDAY AFTERNOON
____________________
Essex Center/South Ballroom
_____________
PAPER
#
2:00
IMAGE PROCESSING ICs
Chairman: L. Christopher
Co-Chairman: S. Law
2:05
The WASP2
WSI
Massively Parallel Processor Demonstrators
17.1
I.P. Jalowiecki, Brunei University, Uxbridge, England; and S.J. Hedge, Aspex Microsystems, Ltd.
2:30
Two-Level Pipelined Systolic Array Graphics Engine
17.2
J.A.K.S. Jayashinghe, G. Karagiannis, F.M. El-Hadidy,
O.E.
Herrmann and J.
Smit,
University of Twente,
Enschede,
The Netherlands
2:55
SVP: Serial Video Processor
17.3
J. Childers, P.
Reinecke,
H.
Miyaguchi,
S.
Yamamoto,
Y.
Takahashi,
Y.
Yaguchi and M. Takeyasu, Texas
Instruments Japan, Ltd., Ibaragi, Japan
3:20
A High Performance SIMD Processor for Binary Image Processor
17.4
J-D.
Legat
and P. DeMuelenaere, Image Recognition Integrated Systems, Louvain-la-Neuve, Belgium
3
:45 A Flexible Motion-Vector Estimation Chip for Real-Time Video Codecs
17.5
K-M. Yang, H. Fujiwara, Y. Ishida, M. Maruyama and T. Sakaguchi, Bellcore,
Momstown,
NJ;
and
H.
Uwabu,
Graphics Communications Technologies, Minato-ku, Japan
4:10
IRIS: A 20MHz Image Recognition Integrated System
17.6
G. Maguire, J. O Brien, M. Finnery, J. Daly, S. Mitchell,
N.
Rida,
J. O Riordan and F. Griffin, Silicon
&
Software
Systems, Dublin, Ireland
4:35
LATE NEWS PAPER
17.7
A Chip-Set for Lossless Image Compression
I. Shah, O. Akiwumi-Assani and B. Johnson, North American Philips Corp., Braircliff Manor, NY
4:50
LATE NEWS PAPER
17.8
A Real-Time Multi-Kernel Picture Convolver
С
Goudet,
Y. Mathieu
and
N.
Demassieux, Telecom Paris University, Paris, France; and G.
Concordel,
TRT
Robinson, France
SESSION
18
TUESDAY AFTERNOON
________________________
America Center Ballroom
________________
PAPER
#
2:00
FABRICATION TECHNOLOGY
&
DEVICE MODELING
Chairman: P. Zeitzoff
Co-Chairman: M. Hartranft
2
:05 A Laser Direct Write Double-Level-Metal Technology for Rapid Fabrication
18.1
C.Y.
Fu,
В.
Law,
R.
Hsu,
R.
Lai,
N.F. Raley,
V. Malba
and
R.
Hills, Lawrence Livermore National
Laboratory,
University of
California, Livermore,
CA
2:30 AllnAs/GalnAsHBT IC
Technology
18.2
J.F.
Jensen,
W.E. Stanchina, R.A. Metzger, D.B. Rensch, M.W.
Pierce,
T.V. Kargodorian and Y.K. Allen, Hughes
Research Laboratories, Malibu, CA
xvii
CONTENTS
2:55 BEST:
A BiCMOS-Composite Super-Self-Aligned ECL Technology
18.3
K.G. Moerschel, W.A.
Possanza,
R.E.
Carsia,
F.M.
Erceg,
C.J. Fassl,
J.C.
Dolcin, J.J. Egan, J.T. Glick, G.R.
Hower, M.P. Ling, R.A. Mantz, G.T. Mazsa, J.A.
Pavlo
and M.A. Prozonic, AT&T Microelectronics, Allentown, PA;
T.Y.
Chiu,
T.Y.M.
Liu, V.D. Archer and R.G. Swartz, AT&TERC, Hopewell, NJ; and K.F.
Lau,
AT&T Bell Labs.,
Princeton, NJ
3:20
A Complementary
SEG
Process and Its Application to Advanced Complementary Bipolar
18.4
Transistors
J.W. Osenbach, H.C. Praefcke, J.P. Gardner, A. Feygenson, A.J. Laduca, J.J. Bastek and J.M. Boyle, AT&T Bell
Labs., Reading, PA
3:45
Precise Capacitor Structure Suitable for
Submicron
Mixed Analog/Digital ASICs
18.5
T. lida,
Toshiba Semiconductor System
Eng.
Center, Kawasaki, Japan; M. Nakahara, S. Gotoh and H. Akiba,
Tobhiba Microelectronics Center, Kawasaki, Japan
4:10
A
0.8
Micron Advanced Single Poly BiCMOS Technology for High Density and High Performance
18.6
Applications
V.
liderem,
A. Iranmanesh, A. Solheim, L. Lam,
С
Blair,
R. Lahri, S. Leíbiger, L,
Bouknight,
M.
Biswal
and
В.
Bastani, National Semiconductor Corp., Puyallup, WA
4:35
Turn-On Transient Imposed Extrinsic Base Consideration in BiNMOS Transistors
18.7
Y-W. Chen and J. Kuo, National Taiwan University, Taipei, Taiwan
5:00
Comparative Performance Limits of MOSFET, MESFET and MODFET Digital Circuits
18.8
V.K.
De
and J.D. Meindl, Rensselaer Polytechnic Institute, Troy, NY
SESSION
19
TUESDAY AFTERNOON
_______________________
Essex North Ballroom
________________
PAPER
#
2:00
RELIABILITY
Chairman: J.S. Runner
Co-Chairman: P. Fasang
2:05
An Integrated ASIC Diagnosis System
19.1
R. Halaviati, K. Jefferson and
N.
Shastry, LSI Logic Corp., Milpitas, CA
2:30
Automotive Electronics
1С
Reliability
19.2
R.J. Straub,
Delco
Electronics Corp., Kokomo, IN
2:55
VLSI Circuit Design with Built-in Reliability Using Simulation Techniques
19.3
W-J Hsu, S.M. Gowda and B.J. Sheu, University of Southern California, Los Angeles, CA
3:20
An integrated System for Circuit Level Hot Carrier Evaluation
19.4
P.G.Y. Tsui,
L
Howington, T. Tiwald, B. Mowry, F.K. Baker, J.D. Hayden, B.B. Feaster and B. Garbs, Motorola,
Inc., Austin,
TX;
and P.M. Lee, University of California, Berkeley, CA
3:45
Novel Fault-Tolerant Circuits for Configurable Mass Memories
19.5
T.P.
Haraszti,
R.P.
Mento
and W.N. Grant, Microcirc Associates, Newport Beach, CA; and AMI-Gould, Pocatello
ID
4:10
Memory System Reliability Improvement Through Associative Cache Redundancy
19.6
M.A.
Lucente,
C.H.
Harris and R.M.
Muir,
The Mitre Corp., Bedford, MA
4:35
LAŢE
NEWS PAPER m7
Estimation of Power Dissipation in CMOS Combinational Circuits
S. Devadas and J. White, MIT, Cambridge,
УА;
and K. Keutzer, AT&T Bell Labs., Murray Hill, NJ
XVI«
CONTENTS
SESSION
20 America South
Ballroom
8:00
TUESDAY EVENING PANEL
Custom
1С
Design Challenge: To Deliver IC s Right, Cheap and On-Time the First Time. Are
You Dreaming?
Moderator: D. Brown, Mitel Corporation
SESSION
21__________________________________
Essex Center/South Ballroo
8:00
TUESDAY EVENING PANEL
Is the Designer of Chip/Wafer Vendor Responsible for Working Designs?
Moderator: K. Venkateswaran, Avasem Corporation
SESSION
22___________________________________
America Center Ballroom
8:00
TUESDAY EVENING PANEL
Rapid Prototyping
:
What Kind of Track is This?
Moderator: A. Barlow, Asahi Kasei Microsystems
SESSION
23_________________________________
Essex North Ballroom
8:00
TUESDAY EVENING PANEL
Large Monolithics vs. Chip Sets
Moderator: A. Roy, Hughes Network Systems
SESSION
24
WEDNESDAY MORNING
________________________
America South Ballroom
_________________
PAPER
#
8:30
HIGH SPEED COMPUTER ELEMENTS
Chairman: J. Buurrna
Co-Chairman: J. Lipman
8:35
A Reconfigurable
Content Addressable Memory
24.1
A.J. McAuley and C.J. Cotton, Bellcore, Morristown, NJ
9:00
A Sub-IOnS Cache SRAM for High Performance
32
Bit Microprocessors
24.2
E.A. Reese and E. Huang, VLSI Technology, Inc., Portland, OR
9:25
A&-rts25&-KbitBiCMOSTTLSRAM
24.3
T. Akioka, A. Hiraishi, T. Yamauchi, Y. Yokoyama, S. Takanashi, M. Iwamura and Y. Kobayashi, Hitachi Ltd.,
Ibaraki, Japan;
A. Ide,
N.
Gotou, K. Onozawa and H. Uchida, Hitachi Ltd., Tokyo, Japan
9:50
Design of VLSI Switch for Highly Parallel Multiprocessor System
24.4
Y. Hsu, C. Benveniste, J. Ruedinger andCJ. Tan, IBM Corp.,
Yorktown
Heights, NY
10:15
A
100
MHz Floating Point/Integer Processor
24.5
G. Taylor, A. Rekow, J. Radke and G. Thompson, Bipolar Integrated Technology, Inc., Beaverton, OR
10:40
Yet Another Multiplier Architecture
24.6
C.C. Stearns and P.H.
Ang,
LSI Logic Corp.,
Mento
Park, CA
XIX
CONTENTS
11:05
A
2.5nS ECL16
x
Multiplier
24.7
S.
Roberts,
W. Snyder,
H.
Chin,
H. Hingarth, S.
Leibiger,
R. Lahri, L. Bouknight and M. Biswal, National
Semiconductor, Puyallup, WA
11:40
LATE NEWS PAPER
24.8
3.5
Gate 32-Bit
ALU
Using GaAs HFET
Technology
W.B.
Leung,
K.W.
Teng,
L.E. Ackner, C.E.
Reid
andT.C.
Poon,
AT&T Bell Labs., Allentown, PA; A.I. Paris and
A.C. Hu, AT&T Bell Labs.,
Reading,
PA; and M. Isbara, Columbia
University,
New York, NY
SESSION 25
WEDNESDAY MORNING
____________________
Essex Center/South Ballroom
_____________
PAPER
#
8:30
HDTV
&
RELATED CIRCUITS
Chairman: C.
Jungo
Co-Chairman: L. Christopher
8:35
A
20
MHz QAM Chip with Numerical Controlled Carrier Generator for Research in HDTV
25.1
M.J. Shumila, David Sarnoff Research Center, Princeton, NJ
9:00
A Video Rate Rerastering
1С 25.2
W.T. Mayweather 111, David Sarnoff Research Center, Princeton, NJ
9:25
A
54
MHz Chip Set for HDTV Filtering
25.3
С
Joanblanq,
F. Rothan
and P.
Senn, CNET-CNS,
Meylan, France
9:50
A
500
MHz Monolithic CRT Video Driver Using a Linear Array
25.4
K.
Kato,
T.
Sase
and
H.
Sato, Hitachi
Ltd., Ibaraki, Japan
10:15
A VLSI DPCM
Encoder/Decoder Chip Set for Extended Quality Digital TV
25.5
A.F. Kwan and R.R. Cordell, Bell Communications Research, Red Bank, NJ
10:40
A General Purpose High Speed Equalizer
25.6
S.
Maginot,
F.
Balestro,
С.
Joanblanq
and P.Senn,
CNET, Meylan,
Cedex,
France; and J. Paticot, CCETT
Rennes,
France
11:05
Fully-Integrated Correlated Tuning
Processor for
Continuous-Time Filters
25.7
P.M. VanPeteghem, T.L. Brooks, W.J. Adams, H.M.
Fossati,
K.H.
Loh,
S. Narayan, G.R. Spalding and R.
Yin,
Texas A&M
University,
Cottege Station,
TX
SESSION
26
WEDNESDAY MORNING
_____________________
America
Center Ballroom
_______________
PAPER
#
8:30
NEURAL
NETWORKS
Chairman:
P.
Ivey
Co-Chairman: F. Yassa
8:35
Implementation of a Neuron Dedicated to Kohonen Maps with Learning Capabilities
26.1
B.
Hochet,
V.
Peins, G.
Corbaz and
M. Deciercq,
Swiss Federal Institute of Technology, Lausanne, Switzerland
9:00
A Novel Switched Capacitor Bidirectional Associative Memory
26.2
B. Maundy, Technical University of Nova Scotia, Halifax, Canada; and E.I. El-Masry, Kuwait University Safat
Kuwait
9:25
A Neurał
Network Integrated Circuit Supporting Programmable Exponent and Mantissa
26.3
H.K. Bropwn,
D.D.
Cross, D.L. Wuerz, Jr., and J.J.
Liou,
University of Central Florida, Orlando, FL
9:50
A Dynamic CMOS Multiplier for Analog Neural Network Cells
26.4
L.W. Massengill, Vanderbift University, Nashville, TN
10:15
A Preprogrammed Artificial Neural Network Architecture in Signal Processing
26.5
J. Bloomer, P. Frank and W.
Engeler,
General Electric, Schenectady, NY
xx
CONTENTS
10:40
A Compact and General-Purpose Neural Chip with Electrically Programmable Synapses
26.6
B.W.
Lee and B.J. Sheu, University of Southern California, Los Angeles, CA
11:05
LATE NEWS PAPER
26.7
Random Address
32
χ
32
Programmable Analog Vector-Matrix Multiplier for Artificial Neural
Networks
K.K. Moon and F.J.
Kub,
Naval Research Lab, Washington, DC; and
I.A.
Mack, Office of Naval Technology, Crystal
City, VA
SESSION
27
WEDNESDAY MORNING
______________________
Essex North Ballroom
________________
PAPER
#
8:30
PLACEMENTS ROUTING TECHNOLOGY
Chairman: M. Tarsi
Co-Chairman:
Н
-F.
Stephen Law
8:35
An Efficient Relative Placement Algorithm for Custom Chip Design
27.1
Z-M. Lin and H.C. Lin, University of Maryland, College Park, MD
9:00
Direct Solution of Performance Constraints During Placement
27.2
A. Chao,
E.
Nequist and
T. Vuong, Cadence
Design Systems, Santa
Clara, CA
9:25
A
Maze Routing Method of Combined Unity and Infinity Expansion Distances
27.3
M-K.
Vai,
G.
Aybay and S-M.
Chu,
Northeastern University, Boston, MA
9:50
Multilayer Area Routing Algorithm as an Optimization Problem
27.4
R. Dutta, A. Roy and R. Rao, Digital Equipment Corp., Hudson, MA
10:15
The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays
27.5
J. Rose and S. Brown, University of Toronto, Toronto, Ontario, Canada
10:40
New Algorithms for Placement and Routing of Custom Analog Cells in ACACIA
27.6
J. Conn, D.J. Garrod, R.A.
Rutenbarand
LR. Carley,
Carnegie Mellon University, Pittsburgh, PA
11:05
A New Routing Method for Full Custom Analog ICs
27.7
S. Piguet, F. Rahali, M. Kayal, E. Zysman and M. Declercq, Swiss Federal Institute of Technology, Lausanne,
Switzerland
XXI
CONTENTS
SESSION
28
WEDNESDAY AFTERNOON
___________________
America South Ballroom
________________
PAPER
#
1:30
TESTING
Chairman: S. Davidson
Co-Chairman: S. Quigley
1
:3S A Toolbox for ASIC Testability Automation
28.1
M.A.
Samad,
VLSI Technology Inc., San Jose, CA
2:00
Testing Embedded RAMs in ASIC Chips
28.2
P.P. Fasang, National Semiconductor Corp., Santa Clara, CA
2:25
A Structured Approach to Macrocell Testing Using Built-in Self-Test
28.3
Y. Zorian, AT&T Bell Labs., Princeton, NJ
2:50
PEST—A Tool for Implementing Pseudo-Exhaustive Self Test
28.4
E. Wu, AT&T Bell Labs., Princeton, NJ
3:15
A Universal Test Sequence for CMOS Scan Registers
28.5
K-J. Lee and M.A.
Breuer,
University of Southern California, Los Angeles, CA
3:40
Defect Analysis and Test Generation for Gate Oxide Shorts in CMOS ICs
28.6
S.i. Syed, Florida Institute of Technology, Melbourne, FL; and
D.M.
Wu, IBM Corp., Boca Raton, FL
4:05
LATE NEWS PAPER
28.7
A Test Strategy for a Bit-Serial VLSI Chip with Analog
IO
S.
Freeman, David Sarnoff Research Center, Princeton, NJ
SESSION
29
WEDNESDAY AFTERNOON
_________________
Essex Center/South Ballroom
_____________
PAPER
#
1:30
LOGIC
&
CIRCUIT SYNTHESIS II
Chairman: S. Cravens
Co-Chairman: D. Daly
1
:35 Boolean Minimization Using New ATPG Techniques and Saved Test Patterns
29.1
C.R. Morrison, VLSI Technology, Valbonne, France
2:00
Exploring the Design Space in High-Level Synthesis
29.2
J. Bhasker, AT&T Bell Labs., Allentown, PA; and M.
Tong,
AT&T
Betl
Labs., Murray Hill, NJ
2:25
Design Assistant: An Expert Tool for ASIC Design
29.3
J-M. Bournazel,
J
-О.
Piednoir, VLSI Technology
euri,
Valbonne, France
2:50
Circuit Partitioning and Resynthesis
29.4
S. Dey
and G. Kedem, Duke University,, Durham, NC;and F. Brglez, The Microelectronics Center of North
Carolina, Research Triangle Park, NC
3:15
Automating the Design of Asynchronous Sequential Logic Circuits
29.5
S-F. Wu and
P.D.
Fisher, Michigan State University, East Lansing, Ml
3:40
Logic Synthesis of Asynchronous Circuits
29.6
C. Piguet, CSEM, Neuchatel, Switzerland
----------------------♦-----------------------
xxii
CONTENTS
SESSION
30
WEDNESDAY AFTERNOON
___________________
America Center Ballroom
_______________
PAPER
#
1
:30 MODULE GENERATION, OPTIMIZATION
&
VERIFICATION
Chairman: K.
Au
Co-Chairman:
S. Mori
1
:35 An Interactive Graphical Approach to Module Generator Development
30.1
D.
Lacroix
and S. Menkis, Cadence Design Systems, San Jose, CA
2:00
STAT:
A Schematic to Artwork Translator for Custom Analog Cells
30.2
S.W.
Mehranfar, Hughes Aircraft Co., Canoga Park, CA
2:25
Hierarchical Symbolic Design Methodology for Large-Scale Datapaths
30.3
K.
Usami,
Y. Sugeno,
N.
Matsumoto and S. Mori,Toshiba Corp., Kawasaki, Japan
2:50
An Interactive/Automatic Floor Planner for Hierarchically Designed Cell Based VLSIs
30.4
T. Hiwatashi and S. Kurosawa, Toshiba Corp., Kawasaki, Japan
3:15
Transformation Based Layout Optimization
30.5
R. Hojati and D-P. Chen, Cadence Design Systems, Santa Clara, CA
3:40
Automatic Verification of Library-Based
1С
Designs
30.6
B.J.S. DeLoore and A.P.
Kostelijk,
Philips Research Labs., Eindhoven, The Netherlands
SESSION
31
WEDNESDAY AFTERNOON
____________________
Essex North Ballroom
________________
PAPER
#
1:30
PROGRAMMABLE LOGIC DEVICES
Chairman: G. Ledenbach
Co-Chairman: W. Carter
1:35
Labyrinth: A Homogeneous Computational Medium
31.1
F.
Furtek,
Concurrent Logic Inc., Arlington, MA; G. Stone and I. Jones, Apple Computer, Inc., Cupertino, CA
2:00
Third-Generation Architecture Boosts Speed and Density of Field-Programmable Gate Arrays
31.2
H.C. Hsieh, W.S. Carter, J.
Ja, E.
Cheung,
С.
Erickson, P. Freidin, L. Tinkey, R. Kanazawa and S.
Schreifels,
Xilinx Inc., San Jose, CA
2:25
An Efficient Logic Block Interconnect Architecture for User-Programmable Gate Array
31.3
K. Kawana, H. Keida, M. Sakamoto, K. Shibata and I. Moriyama, Kawasaki Steel Corp.,
Chiba,
Japan
2:50
The Implementation of Hardware Subroutines on Field Programmable Gate Arrays
31.4
N.
Hastie
and R. Cliff, Plessey
Semiconductora,
Plymouth, England
3:15
An FPGA Family Optimized For High Densities and Reduced Routing Delay
31.5
M. Ahrens, A. EIGamal, D. Galbraith, J. Greene, S. Kaptanoglu, K. Dharmarajan, L. Hutchings,
S. Ku,
P. McGibney,
J. McGowan, A. Sarnie, K. Shaw,
N.
Stiawalt, T. Whitney, T. Wong, W. Wong and B. Wu, Actel Corp., Sunnyvale,
CA
3:40
A 150MHz CMOS EPLD with uW Standby Power
31.6
T. Baueom and M. J. Allen, Intel Corp., Folsom, CA
4:05
LATE NEWS PAPER
31.7
A User Configurable Gate Array Using CMOS-EPROM Technology
A. Gupta, V. Aggarwal, R.
Patel,
P. Cnalasani,
D. Chu,
P. Seeni, P.W. Liu, J. Wu and G. Kaat, Philips Components-
Signetics, Sunnyvale, CA
ХХШ
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| any_adam_object | 1 |
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| dewey-full | 621.3815 |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| spelling | Custom Integrated Circuits Conference 12 1990 Boston, Mass. Verfasser (DE-588)5047671-3 aut Proceedings of the IEEE 1990 Custom Integrated Circuits Conference The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 New York, NY Institute of Electrical and Electronics Engineers 1990 Getr. Zählung zahlr. Ill. u. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1990 Boston Mass. gnd-content Kundenspezifische Schaltung (DE-588)4122250-7 s DE-604 Integrierte Schaltung (DE-588)4027242-4 s 1\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002734333&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings of the IEEE 1990 Custom Integrated Circuits Conference The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 Kundenspezifische Schaltung (DE-588)4122250-7 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4027242-4 (DE-588)1071861417 |
| title | Proceedings of the IEEE 1990 Custom Integrated Circuits Conference The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 |
| title_auth | Proceedings of the IEEE 1990 Custom Integrated Circuits Conference The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 |
| title_exact_search | Proceedings of the IEEE 1990 Custom Integrated Circuits Conference The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 |
| title_full | Proceedings of the IEEE 1990 Custom Integrated Circuits Conference The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 |
| title_fullStr | Proceedings of the IEEE 1990 Custom Integrated Circuits Conference The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 |
| title_full_unstemmed | Proceedings of the IEEE 1990 Custom Integrated Circuits Conference The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 |
| title_short | Proceedings of the IEEE 1990 Custom Integrated Circuits Conference |
| title_sort | proceedings of the ieee 1990 custom integrated circuits conference the westin copley place hotel boston massachusetts may 13 16 1990 |
| title_sub | The Westin Copley Place Hotel Boston, Massachusetts May 13 - 16, 1990 |
| topic | Kundenspezifische Schaltung (DE-588)4122250-7 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Kundenspezifische Schaltung Integrierte Schaltung Konferenzschrift 1990 Boston Mass. |
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