A formal, hierarchical design and validation methodology for VLSI:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Edinburgh
Univ. of Edinburgh, Dep. of Computer Sci.
1988
|
| Schriftenreihe: | University <Edinburgh> / Department of Computer Science: Thesis
55 |
| Schlagworte: | |
| Beschreibung: | Edinburgh, Univ., Diss., 1988 |
| Beschreibung: | 234 S. |
Internformat
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Datensatz im Suchindex
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| id | DE-604.BV004219098 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T16:10:00Z |
| institution | BVB |
| language | English |
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| physical | 234 S. |
| publishDate | 1988 |
| publishDateSearch | 1988 |
| publishDateSort | 1988 |
| publisher | Univ. of Edinburgh, Dep. of Computer Sci. |
| record_format | marc |
| series2 | University <Edinburgh> / Department of Computer Science: Thesis |
| spelling | Davie, Bruce S. Verfasser (DE-588)122327535 aut A formal, hierarchical design and validation methodology for VLSI CST 55 88 Edinburgh Univ. of Edinburgh, Dep. of Computer Sci. 1988 234 S. txt rdacontent n rdamedia nc rdacarrier University <Edinburgh> / Department of Computer Science: Thesis 55 Edinburgh, Univ., Diss., 1988 Circuits sigle Computer software sigle Reliability and quality control sigle Computer-aided design Integrated circuits Very large scale integration (DE-588)4113937-9 Hochschulschrift gnd-content Department of Computer Science: Thesis University <Edinburgh> 55 (DE-604)BV008928181 55 |
| spellingShingle | Davie, Bruce S. A formal, hierarchical design and validation methodology for VLSI Circuits sigle Computer software sigle Reliability and quality control sigle Computer-aided design Integrated circuits Very large scale integration |
| subject_GND | (DE-588)4113937-9 |
| title | A formal, hierarchical design and validation methodology for VLSI |
| title_alt | CST 55 88 |
| title_auth | A formal, hierarchical design and validation methodology for VLSI |
| title_exact_search | A formal, hierarchical design and validation methodology for VLSI |
| title_full | A formal, hierarchical design and validation methodology for VLSI |
| title_fullStr | A formal, hierarchical design and validation methodology for VLSI |
| title_full_unstemmed | A formal, hierarchical design and validation methodology for VLSI |
| title_short | A formal, hierarchical design and validation methodology for VLSI |
| title_sort | a formal hierarchical design and validation methodology for vlsi |
| topic | Circuits sigle Computer software sigle Reliability and quality control sigle Computer-aided design Integrated circuits Very large scale integration |
| topic_facet | Circuits Computer software Reliability and quality control Computer-aided design Integrated circuits Very large scale integration Hochschulschrift |
| volume_link | (DE-604)BV008928181 |
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