Abstract: "The central result of this work is the discovery of a new class of architectures, which I call D-RISC, sharing some characterisctics of both data flow and von Neumann RISC computers, for concurrent computation. This rests on an original and simple theory which relates the demands of...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Clarke, Thomas J. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Cambridge 1989
Schriftenreihe:	Computer Laboratory <Cambridge>: Technical report 174
Schlagworte:	Computer hardware Computer software Information theory Computer architecture Parallel processing (Electronic computers) Hochschulschrift
Zusammenfassung:	Abstract: "The central result of this work is the discovery of a new class of architectures, which I call D-RISC, sharing some characterisctics of both data flow and von Neumann RISC computers, for concurrent computation. This rests on an original and simple theory which relates the demands of concurrent computation on hardware resources to the fundamental performance constraints of technology. I show that dataflow and von Neumann architecture have different fundamental hardware constraints to performance, and that therefore a D-RISC architecture, which balances these two constraints, is likely to be optimum for concurrent computation. The work forms four related section 1) A study of the nature of concurrent symbolic computation and the demands which it makes from any implentation. Two new results emerge from this. A model of computation which will be used extensively in subsequent sections and a way of incorporating imperative updates in a functional language, similar but superior to non-deterministic merge, which captures locally sequential updates in a computation with minimum constraint on global concurrency. 2) The computational model is used to contrast different policies for localising data near a CPU. A new type of cache is proposed which renames all of its cached addresses in order to reduce CPU wordlength 3) CPU design is examined and a new class of architectures for concurrent computation, called D-RISCs, are proposed. 4) The multiple-thread implementation problems encountered in the new architectures are examined. A new analysis of the relationship between scheduling and intermediate store use in a symbolic concurrent computation is presented.
Beschreibung:	Zugl.: Cambridge, Univ., Diss.
Beschreibung:	III, 113 S. graph. Darst.