Mixed systolic arrays: a reconfigurable multiprocessor architecture
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| Main Author: | |
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| Format: | Book |
| Language: | Undetermined |
| Published: |
Ann Arbor, Mich.
Univ. Microfilms International
1984
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| Subjects: | |
| Item Description: | Zugl.: East Lansing, Mich., Michigan State Univ., Diss., 1982 |
| Physical Description: | VIII, 107 S. graph. Darst. |
Staff View
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV003465849 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 900725s1984 d||| m||| 00||| und d | ||
| 035 | |a (OCoLC)631045292 | ||
| 035 | |a (DE-599)BVBBV003465849 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | |a und | ||
| 049 | |a DE-384 | ||
| 084 | |a ST 170 |0 (DE-625)143602: |2 rvk | ||
| 100 | 1 | |a Chang, Tung-Liang |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Mixed systolic arrays |b a reconfigurable multiprocessor architecture |
| 264 | 1 | |a Ann Arbor, Mich. |b Univ. Microfilms International |c 1984 | |
| 300 | |a VIII, 107 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Zugl.: East Lansing, Mich., Michigan State Univ., Diss., 1982 | ||
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 0 | 1 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |D s |
| 689 | 0 | 2 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-002194818 | ||
Record in the Search Index
| _version_ | 1804117811970179072 |
|---|---|
| any_adam_object | |
| author | Chang, Tung-Liang |
| author_facet | Chang, Tung-Liang |
| author_role | aut |
| author_sort | Chang, Tung-Liang |
| author_variant | t l c tlc |
| building | Verbundindex |
| bvnumber | BV003465849 |
| classification_rvk | ST 170 |
| ctrlnum | (OCoLC)631045292 (DE-599)BVBBV003465849 |
| discipline | Informatik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01250nam a2200361 c 4500</leader><controlfield tag="001">BV003465849</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">900725s1984 d||| m||| 00||| und d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)631045292</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV003465849</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-384</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 170</subfield><subfield code="0">(DE-625)143602:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Chang, Tung-Liang</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Mixed systolic arrays</subfield><subfield code="b">a reconfigurable multiprocessor architecture</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Ann Arbor, Mich.</subfield><subfield code="b">Univ. Microfilms International</subfield><subfield code="c">1984</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">VIII, 107 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Zugl.: East Lansing, Mich., Michigan State Univ., Diss., 1982</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-002194818</subfield></datafield></record></collection> |
| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV003465849 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:00:21Z |
| institution | BVB |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002194818 |
| oclc_num | 631045292 |
| open_access_boolean | |
| owner | DE-384 |
| owner_facet | DE-384 |
| physical | VIII, 107 S. graph. Darst. |
| publishDate | 1984 |
| publishDateSearch | 1984 |
| publishDateSort | 1984 |
| publisher | Univ. Microfilms International |
| record_format | marc |
| spelling | Chang, Tung-Liang Verfasser aut Mixed systolic arrays a reconfigurable multiprocessor architecture Ann Arbor, Mich. Univ. Microfilms International 1984 VIII, 107 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Zugl.: East Lansing, Mich., Michigan State Univ., Diss., 1982 Entwurf (DE-588)4121208-3 gnd rswk-swf Mehrprozessorsystem (DE-588)4038397-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Entwurf (DE-588)4121208-3 s Mehrprozessorsystem (DE-588)4038397-0 s VLSI (DE-588)4117388-0 s DE-604 |
| spellingShingle | Chang, Tung-Liang Mixed systolic arrays a reconfigurable multiprocessor architecture Entwurf (DE-588)4121208-3 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4038397-0 (DE-588)4117388-0 (DE-588)4113937-9 |
| title | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_auth | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_exact_search | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_full | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_fullStr | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_full_unstemmed | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_short | Mixed systolic arrays |
| title_sort | mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_sub | a reconfigurable multiprocessor architecture |
| topic | Entwurf (DE-588)4121208-3 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Entwurf Mehrprozessorsystem VLSI Hochschulschrift |
| work_keys_str_mv | AT changtungliang mixedsystolicarraysareconfigurablemultiprocessorarchitecture |