Mixed systolic arrays: a reconfigurable multiprocessor architecture
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
Ann Arbor, Mich.
Univ. Microfilms International
1984
|
| Schlagworte: | |
| Beschreibung: | Zugl.: East Lansing, Mich., Michigan State Univ., Diss., 1982 |
| Beschreibung: | VIII, 107 S. graph. Darst. |
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Datensatz im Suchindex
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| author | Chang, Tung-Liang |
| author_facet | Chang, Tung-Liang |
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| indexdate | 2024-07-09T16:00:21Z |
| institution | BVB |
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| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002194818 |
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| physical | VIII, 107 S. graph. Darst. |
| publishDate | 1984 |
| publishDateSearch | 1984 |
| publishDateSort | 1984 |
| publisher | Univ. Microfilms International |
| record_format | marc |
| spelling | Chang, Tung-Liang Verfasser aut Mixed systolic arrays a reconfigurable multiprocessor architecture Ann Arbor, Mich. Univ. Microfilms International 1984 VIII, 107 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Zugl.: East Lansing, Mich., Michigan State Univ., Diss., 1982 Entwurf (DE-588)4121208-3 gnd rswk-swf Mehrprozessorsystem (DE-588)4038397-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Entwurf (DE-588)4121208-3 s Mehrprozessorsystem (DE-588)4038397-0 s VLSI (DE-588)4117388-0 s DE-604 |
| spellingShingle | Chang, Tung-Liang Mixed systolic arrays a reconfigurable multiprocessor architecture Entwurf (DE-588)4121208-3 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4038397-0 (DE-588)4117388-0 (DE-588)4113937-9 |
| title | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_auth | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_exact_search | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_full | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_fullStr | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_full_unstemmed | Mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_short | Mixed systolic arrays |
| title_sort | mixed systolic arrays a reconfigurable multiprocessor architecture |
| title_sub | a reconfigurable multiprocessor architecture |
| topic | Entwurf (DE-588)4121208-3 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Entwurf Mehrprozessorsystem VLSI Hochschulschrift |
| work_keys_str_mv | AT changtungliang mixedsystolicarraysareconfigurablemultiprocessorarchitecture |