Transistor sizing for timing optimization of combinational digital CMOS circuits:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English German |
| Published: |
Konstanz
Hartung-Gorre
1990
|
| Edition: | 1. Aufl. |
| Series: | Series in microelectronics
4 |
| Subjects: | |
| Item Description: | Zugl.: Zürich, Techn. Hochschule, Diss.. - Zsfassung in dt. Sprache |
| Physical Description: | IX, 102 S. graph. Darst. |
| ISBN: | 3891913303 |
Staff View
MARC
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| 245 | 1 | 0 | |a Transistor sizing for timing optimization of combinational digital CMOS circuits |c Lucas S. Heusler |
| 250 | |a 1. Aufl. | ||
| 264 | 1 | |a Konstanz |b Hartung-Gorre |c 1990 | |
| 300 | |a IX, 102 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 490 | 1 | |a Series in microelectronics |v 4 | |
| 500 | |a Zugl.: Zürich, Techn. Hochschule, Diss.. - Zsfassung in dt. Sprache | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary | |
| 650 | 4 | |a Timing circuits |x Data processing | |
| 650 | 4 | |a Transistor circuits |x Data processing | |
| 650 | 0 | 7 | |a Transistor |0 (DE-588)4060646-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltnetz |0 (DE-588)4052053-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Bemessung |0 (DE-588)4005461-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Nichtlineare Optimierung |0 (DE-588)4128192-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CMOS |0 (DE-588)4010319-5 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
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| 689 | 1 | 1 | |a Transistor |0 (DE-588)4060646-6 |D s |
| 689 | 1 | 2 | |a Bemessung |0 (DE-588)4005461-5 |D s |
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Record in the Search Index
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|---|---|
| any_adam_object | |
| author | Heusler, Lucas S. |
| author_facet | Heusler, Lucas S. |
| author_role | aut |
| author_sort | Heusler, Lucas S. |
| author_variant | l s h ls lsh |
| building | Verbundindex |
| bvnumber | BV002603080 |
| callnumber-first | T - Technology |
| callnumber-label | TK7871 |
| callnumber-raw | TK7871.99.M44 |
| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| classification_tum | ELT 364d ELT 456d |
| ctrlnum | (OCoLC)23142425 (DE-599)BVBBV002603080 |
| dewey-full | 621.39/732 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/732 |
| dewey-search | 621.39/732 |
| dewey-sort | 3621.39 3732 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 1. Aufl. |
| format | Book |
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| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV002603080 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T15:47:17Z |
| institution | BVB |
| isbn | 3891913303 |
| language | English German |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-001675641 |
| oclc_num | 23142425 |
| open_access_boolean | |
| owner | DE-Aug4 DE-91 DE-BY-TUM |
| owner_facet | DE-Aug4 DE-91 DE-BY-TUM |
| physical | IX, 102 S. graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| publisher | Hartung-Gorre |
| record_format | marc |
| series | Series in microelectronics |
| series2 | Series in microelectronics |
| spelling | Heusler, Lucas S. Verfasser aut Transistor sizing for timing optimization of combinational digital CMOS circuits Lucas S. Heusler 1. Aufl. Konstanz Hartung-Gorre 1990 IX, 102 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Series in microelectronics 4 Zugl.: Zürich, Techn. Hochschule, Diss.. - Zsfassung in dt. Sprache Datenverarbeitung Metal oxide semiconductors, Complementary Timing circuits Data processing Transistor circuits Data processing Transistor (DE-588)4060646-6 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf Schaltnetz (DE-588)4052053-5 gnd rswk-swf Bemessung (DE-588)4005461-5 gnd rswk-swf Nichtlineare Optimierung (DE-588)4128192-5 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Schaltnetz (DE-588)4052053-5 s CMOS (DE-588)4010319-5 s Transistor (DE-588)4060646-6 s Nichtlineare Optimierung (DE-588)4128192-5 s DE-604 CMOS-Schaltung (DE-588)4148111-2 s Bemessung (DE-588)4005461-5 s Series in microelectronics 4 (DE-604)BV002454417 4 |
| spellingShingle | Heusler, Lucas S. Transistor sizing for timing optimization of combinational digital CMOS circuits Series in microelectronics Datenverarbeitung Metal oxide semiconductors, Complementary Timing circuits Data processing Transistor circuits Data processing Transistor (DE-588)4060646-6 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Schaltnetz (DE-588)4052053-5 gnd Bemessung (DE-588)4005461-5 gnd Nichtlineare Optimierung (DE-588)4128192-5 gnd CMOS (DE-588)4010319-5 gnd |
| subject_GND | (DE-588)4060646-6 (DE-588)4148111-2 (DE-588)4052053-5 (DE-588)4005461-5 (DE-588)4128192-5 (DE-588)4010319-5 (DE-588)4113937-9 |
| title | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_auth | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_exact_search | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_full | Transistor sizing for timing optimization of combinational digital CMOS circuits Lucas S. Heusler |
| title_fullStr | Transistor sizing for timing optimization of combinational digital CMOS circuits Lucas S. Heusler |
| title_full_unstemmed | Transistor sizing for timing optimization of combinational digital CMOS circuits Lucas S. Heusler |
| title_short | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_sort | transistor sizing for timing optimization of combinational digital cmos circuits |
| topic | Datenverarbeitung Metal oxide semiconductors, Complementary Timing circuits Data processing Transistor circuits Data processing Transistor (DE-588)4060646-6 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Schaltnetz (DE-588)4052053-5 gnd Bemessung (DE-588)4005461-5 gnd Nichtlineare Optimierung (DE-588)4128192-5 gnd CMOS (DE-588)4010319-5 gnd |
| topic_facet | Datenverarbeitung Metal oxide semiconductors, Complementary Timing circuits Data processing Transistor circuits Data processing Transistor CMOS-Schaltung Schaltnetz Bemessung Nichtlineare Optimierung CMOS Hochschulschrift |
| volume_link | (DE-604)BV002454417 |
| work_keys_str_mv | AT heuslerlucass transistorsizingfortimingoptimizationofcombinationaldigitalcmoscircuits |