APA (7th ed.) Citation

Heusler, L. S. (1990). Transistor sizing for timing optimization of combinational digital CMOS circuits (1. Aufl.). Hartung-Gorre.

Chicago Style (17th ed.) Citation

Heusler, Lucas S. Transistor Sizing for Timing Optimization of Combinational Digital CMOS Circuits. 1. Aufl. Konstanz: Hartung-Gorre, 1990.

MLA (9th ed.) Citation

Heusler, Lucas S. Transistor Sizing for Timing Optimization of Combinational Digital CMOS Circuits. 1. Aufl. Hartung-Gorre, 1990.