Logic testing and design for testability:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cambridge, Mass. u.a.
MIT Press
1985
|
| Schriftenreihe: | The MIT Press series in computer systems
|
| Schlagworte: | |
| Beschreibung: | X, 284 S. graph. Darst. |
| ISBN: | 0262060965 |
Internformat
MARC
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| 245 | 1 | 0 | |a Logic testing and design for testability |c Hideo, Fujiwara |
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Datensatz im Suchindex
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| any_adam_object | |
| author | Fujiwara, Hideo |
| author_facet | Fujiwara, Hideo |
| author_role | aut |
| author_sort | Fujiwara, Hideo |
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| building | Verbundindex |
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| ctrlnum | (OCoLC)11650168 (DE-599)BVBBV002300991 |
| dewey-full | 621.395 621.3815/37 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 621.3815/37 |
| dewey-search | 621.395 621.3815/37 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV002300991 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T15:43:39Z |
| institution | BVB |
| isbn | 0262060965 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-001512222 |
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| physical | X, 284 S. graph. Darst. |
| publishDate | 1985 |
| publishDateSearch | 1985 |
| publishDateSort | 1985 |
| publisher | MIT Press |
| record_format | marc |
| series2 | The MIT Press series in computer systems |
| spelling | Fujiwara, Hideo Verfasser aut Logic testing and design for testability Hideo, Fujiwara Cambridge, Mass. u.a. MIT Press 1985 X, 284 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The MIT Press series in computer systems Circuits logiques - Essais Logic circuits Testing VLSI (DE-588)4117388-0 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf VLSI (DE-588)4117388-0 s Test (DE-588)4059549-3 s DE-604 Integrierte Schaltung (DE-588)4027242-4 s Logische Schaltung (DE-588)4131023-8 s 1\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Fujiwara, Hideo Logic testing and design for testability Circuits logiques - Essais Logic circuits Testing VLSI (DE-588)4117388-0 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Logische Schaltung (DE-588)4131023-8 gnd Test (DE-588)4059549-3 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4027242-4 (DE-588)4131023-8 (DE-588)4059549-3 |
| title | Logic testing and design for testability |
| title_auth | Logic testing and design for testability |
| title_exact_search | Logic testing and design for testability |
| title_full | Logic testing and design for testability Hideo, Fujiwara |
| title_fullStr | Logic testing and design for testability Hideo, Fujiwara |
| title_full_unstemmed | Logic testing and design for testability Hideo, Fujiwara |
| title_short | Logic testing and design for testability |
| title_sort | logic testing and design for testability |
| topic | Circuits logiques - Essais Logic circuits Testing VLSI (DE-588)4117388-0 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Logische Schaltung (DE-588)4131023-8 gnd Test (DE-588)4059549-3 gnd |
| topic_facet | Circuits logiques - Essais Logic circuits Testing VLSI Integrierte Schaltung Logische Schaltung Test |
| work_keys_str_mv | AT fujiwarahideo logictestinganddesignfortestability |