Process and Device Modeling for Integrated Circuit Design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Louvain
Universite Catholique de Louvain
1977
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| Beschreibung: | 1 Band Illustrationen, Diagramme |
Internformat
MARC
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| 245 | 1 | 0 | |a Process and Device Modeling for Integrated Circuit Design |c D. Widmann, Research Laboratories, Siemens AG, München, F. R. Germany |
| 246 | 1 | 3 | |a NATO Advanced Study Institute on Process and Device Modeling for Integrated Circuit Design |
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| 505 | 8 | 0 | |t Pattern generation for integrated circuit fabrication |t Fundamental limits in integrated circuits |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-001366263 | ||
Datensatz im Suchindex
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|---|---|
| any_adam_object | |
| author | Widmann, D. |
| author_facet | Widmann, D. |
| author_role | aut |
| author_sort | Widmann, D. |
| author_variant | d w dw |
| building | Verbundindex |
| bvnumber | BV002086594 |
| contents | Pattern generation for integrated circuit fabrication Fundamental limits in integrated circuits |
| ctrlnum | (OCoLC)630230142 (DE-599)BVBBV002086594 |
| format | Book |
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| id | DE-604.BV002086594 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T15:40:06Z |
| institution | BVB |
| language | English |
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| oclc_num | 630230142 |
| open_access_boolean | |
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| owner_facet | DE-91 DE-BY-TUM |
| physical | 1 Band Illustrationen, Diagramme |
| publishDate | 1977 |
| publishDateSearch | 1977 |
| publishDateSort | 1977 |
| publisher | Universite Catholique de Louvain |
| record_format | marc |
| spelling | Widmann, D. Verfasser aut Process and Device Modeling for Integrated Circuit Design D. Widmann, Research Laboratories, Siemens AG, München, F. R. Germany NATO Advanced Study Institute on Process and Device Modeling for Integrated Circuit Design Louvain Universite Catholique de Louvain 1977 1 Band Illustrationen, Diagramme txt rdacontent n rdamedia nc rdacarrier Pattern generation for integrated circuit fabrication Fundamental limits in integrated circuits |
| spellingShingle | Widmann, D. Process and Device Modeling for Integrated Circuit Design Pattern generation for integrated circuit fabrication Fundamental limits in integrated circuits |
| title | Process and Device Modeling for Integrated Circuit Design |
| title_alt | NATO Advanced Study Institute on Process and Device Modeling for Integrated Circuit Design Pattern generation for integrated circuit fabrication Fundamental limits in integrated circuits |
| title_auth | Process and Device Modeling for Integrated Circuit Design |
| title_exact_search | Process and Device Modeling for Integrated Circuit Design |
| title_full | Process and Device Modeling for Integrated Circuit Design D. Widmann, Research Laboratories, Siemens AG, München, F. R. Germany |
| title_fullStr | Process and Device Modeling for Integrated Circuit Design D. Widmann, Research Laboratories, Siemens AG, München, F. R. Germany |
| title_full_unstemmed | Process and Device Modeling for Integrated Circuit Design D. Widmann, Research Laboratories, Siemens AG, München, F. R. Germany |
| title_short | Process and Device Modeling for Integrated Circuit Design |
| title_sort | process and device modeling for integrated circuit design |
| work_keys_str_mv | AT widmannd processanddevicemodelingforintegratedcircuitdesign AT widmannd natoadvancedstudyinstituteonprocessanddevicemodelingforintegratedcircuitdesign |