Sensitivity and optimization:
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Buch |
Sprache: | English |
Veröffentlicht: |
Amsterdam (u.a.)
Elsevier
1980
|
Schriftenreihe: | Computer-aided design of electronic circuits.
2. |
Schlagworte: | |
Beschreibung: | XII, 368 S. graph. Darst. |
ISBN: | 0444419292 |
Internformat
MARC
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100 | 1 | |a Brayton, Robert K. |e Verfasser |4 aut | |
245 | 1 | 0 | |a Sensitivity and optimization |c Robert K. Brayton ; Robert Spence* |
264 | 1 | |a Amsterdam (u.a.) |b Elsevier |c 1980 | |
300 | |a XII, 368 S. |b graph. Darst. | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
490 | 1 | |a Computer-aided design of electronic circuits. |v 2. | |
650 | 4 | |a Datenverarbeitung | |
650 | 4 | |a Electronic circuit design |x Data processing | |
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650 | 0 | 7 | |a Simulation |0 (DE-588)4055072-2 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
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Datensatz im Suchindex
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---|---|
any_adam_object | |
author | Brayton, Robert K. Spence, Robert |
author_facet | Brayton, Robert K. Spence, Robert |
author_role | aut aut |
author_sort | Brayton, Robert K. |
author_variant | r k b rk rkb r s rs |
building | Verbundindex |
bvnumber | BV002009797 |
callnumber-first | T - Technology |
callnumber-label | TK7867 |
callnumber-raw | TK7867 |
callnumber-search | TK7867 |
callnumber-sort | TK 47867 |
callnumber-subject | TK - Electrical and Nuclear Engineering |
classification_rvk | SK 950 |
ctrlnum | (OCoLC)6735434 (DE-599)BVBBV002009797 |
dewey-full | 621.3815/3 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815/3 |
dewey-search | 621.3815/3 |
dewey-sort | 3621.3815 13 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Mathematik Elektrotechnik / Elektronik / Nachrichtentechnik |
format | Book |
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id | DE-604.BV002009797 |
illustrated | Illustrated |
indexdate | 2024-07-09T15:38:49Z |
institution | BVB |
isbn | 0444419292 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-001311516 |
oclc_num | 6735434 |
open_access_boolean | |
owner | DE-91 DE-BY-TUM DE-384 DE-29T |
owner_facet | DE-91 DE-BY-TUM DE-384 DE-29T |
physical | XII, 368 S. graph. Darst. |
publishDate | 1980 |
publishDateSearch | 1980 |
publishDateSort | 1980 |
publisher | Elsevier |
record_format | marc |
series | Computer-aided design of electronic circuits. |
series2 | Computer-aided design of electronic circuits. |
spelling | Brayton, Robert K. Verfasser aut Sensitivity and optimization Robert K. Brayton ; Robert Spence* Amsterdam (u.a.) Elsevier 1980 XII, 368 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Computer-aided design of electronic circuits. 2. Datenverarbeitung Electronic circuit design Data processing Sensitivitätsanalyse (DE-588)4129730-1 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Netzwerkanalyse (DE-588)4075298-7 gnd rswk-swf Simulation (DE-588)4055072-2 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 s Sensitivitätsanalyse (DE-588)4129730-1 s DE-604 Simulation (DE-588)4055072-2 s 1\p DE-604 Schaltungsentwurf (DE-588)4179389-4 s 2\p DE-604 Netzwerkanalyse (DE-588)4075298-7 s 3\p DE-604 CAD (DE-588)4069794-0 s 4\p DE-604 Spence, Robert Verfasser aut Computer-aided design of electronic circuits. 2. (DE-604)BV001901093 2. 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Brayton, Robert K. Spence, Robert Sensitivity and optimization Computer-aided design of electronic circuits. Datenverarbeitung Electronic circuit design Data processing Sensitivitätsanalyse (DE-588)4129730-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd CAD (DE-588)4069794-0 gnd Netzwerkanalyse (DE-588)4075298-7 gnd Simulation (DE-588)4055072-2 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
subject_GND | (DE-588)4129730-1 (DE-588)4179389-4 (DE-588)4069794-0 (DE-588)4075298-7 (DE-588)4055072-2 (DE-588)4168051-0 |
title | Sensitivity and optimization |
title_auth | Sensitivity and optimization |
title_exact_search | Sensitivity and optimization |
title_full | Sensitivity and optimization Robert K. Brayton ; Robert Spence* |
title_fullStr | Sensitivity and optimization Robert K. Brayton ; Robert Spence* |
title_full_unstemmed | Sensitivity and optimization Robert K. Brayton ; Robert Spence* |
title_short | Sensitivity and optimization |
title_sort | sensitivity and optimization |
topic | Datenverarbeitung Electronic circuit design Data processing Sensitivitätsanalyse (DE-588)4129730-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd CAD (DE-588)4069794-0 gnd Netzwerkanalyse (DE-588)4075298-7 gnd Simulation (DE-588)4055072-2 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
topic_facet | Datenverarbeitung Electronic circuit design Data processing Sensitivitätsanalyse Schaltungsentwurf CAD Netzwerkanalyse Simulation Logischer Entwurf |
volume_link | (DE-604)BV001901093 |
work_keys_str_mv | AT braytonrobertk sensitivityandoptimization AT spencerobert sensitivityandoptimization |