Computer systems architecture:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
London u.a.
Pitman
1980
|
| Ausgabe: | 1. publ. |
| Schlagworte: | |
| Beschreibung: | XIII,626 S. zahlr.graph.Darst. |
| ISBN: | 0914894153 0273014749 |
Internformat
MARC
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| 100 | 1 | |a Baer, Jean-Loup |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Computer systems architecture |
| 250 | |a 1. publ. | ||
| 264 | 1 | |a London u.a. |b Pitman |c 1980 | |
| 300 | |a XIII,626 S. |b zahlr.graph.Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 7 | |a Computerarchitectuur |2 gtt | |
| 650 | 7 | |a Computersystemen |2 gtt | |
| 650 | 7 | |a algorithme arithmétique |2 inriac | |
| 650 | 7 | |a architecture ordinateur |2 inriac | |
| 650 | 7 | |a entrée-sortie |2 inriac | |
| 650 | 7 | |a gestion mémoire |2 inriac | |
| 650 | 7 | |a hiérarchie mémoire |2 inriac | |
| 650 | 7 | |a microprocesseur |2 inriac | |
| 650 | 7 | |a microprogrammation |2 inriac | |
| 650 | 7 | |a processeur central |2 inriac | |
| 650 | 7 | |a prospective architecture ordinateur |2 inriac | |
| 650 | 7 | |a super-calculateur |2 inriac | |
| 650 | 7 | |a unité commande |2 inriac | |
| 650 | 4 | |a Computer architecture | |
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| 650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
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Datensatz im Suchindex
| _version_ | 1804116444875587584 |
|---|---|
| any_adam_object | |
| author | Baer, Jean-Loup |
| author_facet | Baer, Jean-Loup |
| author_role | aut |
| author_sort | Baer, Jean-Loup |
| author_variant | j l b jlb |
| building | Verbundindex |
| bvnumber | BV001997556 |
| callnumber-first | Q - Science |
| callnumber-label | QA76 |
| callnumber-raw | QA76 |
| callnumber-search | QA76 |
| callnumber-sort | QA 276 |
| callnumber-subject | QA - Mathematics |
| classification_rvk | ST 150 |
| ctrlnum | (OCoLC)7134315 (DE-599)BVBBV001997556 |
| dewey-full | 001.64 004.22 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 001 - Knowledge 004 - Computer science |
| dewey-raw | 001.64 004.22 |
| dewey-search | 001.64 004.22 |
| dewey-sort | 11.64 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Allgemeines Informatik |
| edition | 1. publ. |
| format | Book |
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| id | DE-604.BV001997556 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T15:38:37Z |
| institution | BVB |
| isbn | 0914894153 0273014749 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-001303024 |
| oclc_num | 7134315 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-29T |
| owner_facet | DE-91G DE-BY-TUM DE-29T |
| physical | XIII,626 S. zahlr.graph.Darst. |
| publishDate | 1980 |
| publishDateSearch | 1980 |
| publishDateSort | 1980 |
| publisher | Pitman |
| record_format | marc |
| spelling | Baer, Jean-Loup Verfasser aut Computer systems architecture 1. publ. London u.a. Pitman 1980 XIII,626 S. zahlr.graph.Darst. txt rdacontent n rdamedia nc rdacarrier Computerarchitectuur gtt Computersystemen gtt algorithme arithmétique inriac architecture ordinateur inriac entrée-sortie inriac gestion mémoire inriac hiérarchie mémoire inriac microprocesseur inriac microprogrammation inriac processeur central inriac prospective architecture ordinateur inriac super-calculateur inriac unité commande inriac Computer architecture Systementwicklung (DE-588)4126945-7 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 s DE-604 Systementwicklung (DE-588)4126945-7 s 1\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Baer, Jean-Loup Computer systems architecture Computerarchitectuur gtt Computersystemen gtt algorithme arithmétique inriac architecture ordinateur inriac entrée-sortie inriac gestion mémoire inriac hiérarchie mémoire inriac microprocesseur inriac microprogrammation inriac processeur central inriac prospective architecture ordinateur inriac super-calculateur inriac unité commande inriac Computer architecture Systementwicklung (DE-588)4126945-7 gnd Computerarchitektur (DE-588)4048717-9 gnd |
| subject_GND | (DE-588)4126945-7 (DE-588)4048717-9 |
| title | Computer systems architecture |
| title_auth | Computer systems architecture |
| title_exact_search | Computer systems architecture |
| title_full | Computer systems architecture |
| title_fullStr | Computer systems architecture |
| title_full_unstemmed | Computer systems architecture |
| title_short | Computer systems architecture |
| title_sort | computer systems architecture |
| topic | Computerarchitectuur gtt Computersystemen gtt algorithme arithmétique inriac architecture ordinateur inriac entrée-sortie inriac gestion mémoire inriac hiérarchie mémoire inriac microprocesseur inriac microprogrammation inriac processeur central inriac prospective architecture ordinateur inriac super-calculateur inriac unité commande inriac Computer architecture Systementwicklung (DE-588)4126945-7 gnd Computerarchitektur (DE-588)4048717-9 gnd |
| topic_facet | Computerarchitectuur Computersystemen algorithme arithmétique architecture ordinateur entrée-sortie gestion mémoire hiérarchie mémoire microprocesseur microprogrammation processeur central prospective architecture ordinateur super-calculateur unité commande Computer architecture Systementwicklung Computerarchitektur |
| work_keys_str_mv | AT baerjeanloup computersystemsarchitecture |