Reconfigurable computing :: the theory and practice of FPGA-based computation /
The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in...
Gespeichert in:
| Weitere Verfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam ; Boston :
Morgan Kaufmann,
©2008.
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon.
|
| Schlagworte: | |
| Online-Zugang: | Volltext Volltext |
| Zusammenfassung: | The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches. This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or computing vehicles to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes Views of FPGA programming beyond Verilog/VHDL Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways. |
| Beschreibung: | 1 online resource (xxix, 908 pages) : illustrations |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9780123705228 0123705223 9780080556017 0080556019 |
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| 245 | 0 | 0 | |a Reconfigurable computing : |b the theory and practice of FPGA-based computation / |c edited by Scott Hauck and André DeHon. |
| 260 | |a Amsterdam ; |a Boston : |b Morgan Kaufmann, |c ©2008. | ||
| 300 | |a 1 online resource (xxix, 908 pages) : |b illustrations | ||
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| 490 | 1 | |a The Morgan Kaufmann series in systems on silicon | |
| 520 | |a The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches. This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or computing vehicles to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes Views of FPGA programming beyond Verilog/VHDL Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways. | ||
| 505 | 0 | |a Contents -- Preface -- Introduction -- Part One: Hardware -- Part I INTRO -- Chapter 1 -- General-Purpose FPGA Architecture -- Chapter 2 -- Reconfigurable Computing Devices -- Chapter 3 -- Reconfigurable Computing Systems -- Chapter 4 -- Reconfiguration Management -- Part Two: Software -- Part II Intro -- Chapter 5 -- Computer Models and System Architectures -- Andř DeHon Chapter 6 -- Hardware Description Languages (VHDL) -- Chapter 7 -- Compilation for Reconfigurable Computing Machines -- Chapter 8 -- Streaming Models -- 8.1 MATLAB/SIMULINK -- 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 -- OS/Runtime Systems -- Chapter 11 -- JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 -- Placement -- 13.1 General-purpose / FPGA -- 13.2 Datapath -- 13.3 Constructive -- Chapter 14 -- Routing -- Chapter 15 -- Retimin -- Chapter 16 -- Bitstream Generation, JBits -- Chapter 17 -- Fast Mapping -- Part Three: Application Development -- PART III INTRO -- Chapter 18 -- Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 -- Precision Analysis & Floating Point -- Chapter 21 -- Distributed Arithmetic -- Chapter 22 -- CORDIC -- Chapter 23 -- Task allocation: FPGA vs. CPU partitioning -- Part Four: Case Studies -- PART IV INTRO -- Chapter 24 -- Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 -- Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 -- Problem-specific circuitry: SAT Solving -- Chapter 27 -- Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 -- FDTD -- Chapter 30 -- Genetic Evolution -- Chapter 31 -- Packet Filtering (Networking application) -- Chapter 32 -- Active Pages [Memory centric] -- Part Five: Theoretical Underpinnings and Future Directions -- PART V INTRO -- Chapter 33- Theoretical Underpinnings, Metrics and Analysis -- Chapter 34 -- Defect and Fault Tolerance -- Chapter 35 -- Reconfigurable Computing and Nanotechnology. | |
| 504 | |a Includes bibliographical references and index. | ||
| 588 | 0 | |a Print version record. | |
| 650 | 0 | |a Adaptive computing systems. |0 http://id.loc.gov/authorities/subjects/sh2002012109 | |
| 650 | 0 | |a Field programmable gate arrays. |0 http://id.loc.gov/authorities/subjects/sh93009062 | |
| 650 | 6 | |a Systèmes adaptatifs (Informatique) | |
| 650 | 6 | |a Réseaux logiques programmables par l'utilisateur. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
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| 655 | 7 | |a Thèses et écrits académiques. |2 rvmgf | |
| 700 | 1 | |a Hauck, Scott. |0 http://id.loc.gov/authorities/names/n2007050398 | |
| 700 | 1 | |a DeHon, André. |0 http://id.loc.gov/authorities/names/n2007050400 | |
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| contents | Contents -- Preface -- Introduction -- Part One: Hardware -- Part I INTRO -- Chapter 1 -- General-Purpose FPGA Architecture -- Chapter 2 -- Reconfigurable Computing Devices -- Chapter 3 -- Reconfigurable Computing Systems -- Chapter 4 -- Reconfiguration Management -- Part Two: Software -- Part II Intro -- Chapter 5 -- Computer Models and System Architectures -- Andř DeHon Chapter 6 -- Hardware Description Languages (VHDL) -- Chapter 7 -- Compilation for Reconfigurable Computing Machines -- Chapter 8 -- Streaming Models -- 8.1 MATLAB/SIMULINK -- 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 -- OS/Runtime Systems -- Chapter 11 -- JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 -- Placement -- 13.1 General-purpose / FPGA -- 13.2 Datapath -- 13.3 Constructive -- Chapter 14 -- Routing -- Chapter 15 -- Retimin -- Chapter 16 -- Bitstream Generation, JBits -- Chapter 17 -- Fast Mapping -- Part Three: Application Development -- PART III INTRO -- Chapter 18 -- Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 -- Precision Analysis & Floating Point -- Chapter 21 -- Distributed Arithmetic -- Chapter 22 -- CORDIC -- Chapter 23 -- Task allocation: FPGA vs. CPU partitioning -- Part Four: Case Studies -- PART IV INTRO -- Chapter 24 -- Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 -- Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 -- Problem-specific circuitry: SAT Solving -- Chapter 27 -- Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 -- FDTD -- Chapter 30 -- Genetic Evolution -- Chapter 31 -- Packet Filtering (Networking application) -- Chapter 32 -- Active Pages [Memory centric] -- Part Five: Theoretical Underpinnings and Future Directions -- PART V INTRO -- Chapter 33- Theoretical Underpinnings, Metrics and Analysis -- Chapter 34 -- Defect and Fault Tolerance -- Chapter 35 -- Reconfigurable Computing and Nanotechnology. |
| ctrlnum | (OCoLC)228148323 |
| dewey-full | 621.39/5 |
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| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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code="c">©2008.</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xxix, 908 pages) :</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">computer</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">online resource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">The Morgan Kaufmann series in systems on silicon</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches. This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or computing vehicles to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes Views of FPGA programming beyond Verilog/VHDL Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways.</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Contents -- Preface -- Introduction -- Part One: Hardware -- Part I INTRO -- Chapter 1 -- General-Purpose FPGA Architecture -- Chapter 2 -- Reconfigurable Computing Devices -- Chapter 3 -- Reconfigurable Computing Systems -- Chapter 4 -- Reconfiguration Management -- Part Two: Software -- Part II Intro -- Chapter 5 -- Computer Models and System Architectures -- Andř DeHon Chapter 6 -- Hardware Description Languages (VHDL) -- Chapter 7 -- Compilation for Reconfigurable Computing Machines -- Chapter 8 -- Streaming Models -- 8.1 MATLAB/SIMULINK -- 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 -- OS/Runtime Systems -- Chapter 11 -- JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 -- Placement -- 13.1 General-purpose / FPGA -- 13.2 Datapath -- 13.3 Constructive -- Chapter 14 -- Routing -- Chapter 15 -- Retimin -- Chapter 16 -- Bitstream Generation, JBits -- Chapter 17 -- Fast Mapping -- Part Three: Application Development -- PART III INTRO -- Chapter 18 -- Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 -- Precision Analysis & Floating Point -- Chapter 21 -- Distributed Arithmetic -- Chapter 22 -- CORDIC -- Chapter 23 -- Task allocation: FPGA vs. CPU partitioning -- Part Four: Case Studies -- PART IV INTRO -- Chapter 24 -- Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 -- Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 -- Problem-specific circuitry: SAT Solving -- Chapter 27 -- Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 -- FDTD -- Chapter 30 -- Genetic Evolution -- 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| genre | Aufsatzsammlung. swd dissertations. aat Academic theses fast Academic theses. lcgft http://id.loc.gov/authorities/genreForms/gf2014026039 Thèses et écrits académiques. rvmgf |
| genre_facet | Aufsatzsammlung. dissertations. Academic theses Academic theses. Thèses et écrits académiques. |
| id | ZDB-4-EBA-ocn228148323 |
| illustrated | Illustrated |
| indexdate | 2024-11-27T13:16:21Z |
| institution | BVB |
| isbn | 9780123705228 0123705223 9780080556017 0080556019 |
| language | English |
| oclc_num | 228148323 |
| open_access_boolean | |
| owner | MAIN DE-863 DE-BY-FWS |
| owner_facet | MAIN DE-863 DE-BY-FWS |
| physical | 1 online resource (xxix, 908 pages) : illustrations |
| psigel | ZDB-4-EBA |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Morgan Kaufmann, |
| record_format | marc |
| series | Morgan Kaufmann series in systems on silicon. |
| series2 | The Morgan Kaufmann series in systems on silicon |
| spelling | Reconfigurable computing : the theory and practice of FPGA-based computation / edited by Scott Hauck and André DeHon. Amsterdam ; Boston : Morgan Kaufmann, ©2008. 1 online resource (xxix, 908 pages) : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier The Morgan Kaufmann series in systems on silicon The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches. This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or computing vehicles to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes Views of FPGA programming beyond Verilog/VHDL Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways. Contents -- Preface -- Introduction -- Part One: Hardware -- Part I INTRO -- Chapter 1 -- General-Purpose FPGA Architecture -- Chapter 2 -- Reconfigurable Computing Devices -- Chapter 3 -- Reconfigurable Computing Systems -- Chapter 4 -- Reconfiguration Management -- Part Two: Software -- Part II Intro -- Chapter 5 -- Computer Models and System Architectures -- Andř DeHon Chapter 6 -- Hardware Description Languages (VHDL) -- Chapter 7 -- Compilation for Reconfigurable Computing Machines -- Chapter 8 -- Streaming Models -- 8.1 MATLAB/SIMULINK -- 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 -- OS/Runtime Systems -- Chapter 11 -- JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 -- Placement -- 13.1 General-purpose / FPGA -- 13.2 Datapath -- 13.3 Constructive -- Chapter 14 -- Routing -- Chapter 15 -- Retimin -- Chapter 16 -- Bitstream Generation, JBits -- Chapter 17 -- Fast Mapping -- Part Three: Application Development -- PART III INTRO -- Chapter 18 -- Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 -- Precision Analysis & Floating Point -- Chapter 21 -- Distributed Arithmetic -- Chapter 22 -- CORDIC -- Chapter 23 -- Task allocation: FPGA vs. CPU partitioning -- Part Four: Case Studies -- PART IV INTRO -- Chapter 24 -- Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 -- Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 -- Problem-specific circuitry: SAT Solving -- Chapter 27 -- Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 -- FDTD -- Chapter 30 -- Genetic Evolution -- Chapter 31 -- Packet Filtering (Networking application) -- Chapter 32 -- Active Pages [Memory centric] -- Part Five: Theoretical Underpinnings and Future Directions -- PART V INTRO -- Chapter 33- Theoretical Underpinnings, Metrics and Analysis -- Chapter 34 -- Defect and Fault Tolerance -- Chapter 35 -- Reconfigurable Computing and Nanotechnology. Includes bibliographical references and index. Print version record. Adaptive computing systems. http://id.loc.gov/authorities/subjects/sh2002012109 Field programmable gate arrays. http://id.loc.gov/authorities/subjects/sh93009062 Systèmes adaptatifs (Informatique) Réseaux logiques programmables par l'utilisateur. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Adaptive computing systems fast Field programmable gate arrays fast Computerarchitektur gnd http://d-nb.info/gnd/4048717-9 Field programmable gate array gnd http://d-nb.info/gnd/4347749-5 Rekonfiguration gnd http://d-nb.info/gnd/4306238-6 Aufsatzsammlung. swd dissertations. aat Academic theses fast Academic theses. lcgft http://id.loc.gov/authorities/genreForms/gf2014026039 Thèses et écrits académiques. rvmgf Hauck, Scott. http://id.loc.gov/authorities/names/n2007050398 DeHon, André. http://id.loc.gov/authorities/names/n2007050400 has work: Reconfigurable computing (Text) https://id.oclc.org/worldcat/entity/E39PCFvmCjDMqQy4YvT9DKKfdP https://id.oclc.org/worldcat/ontology/hasWork Print version: Reconfigurable computing. Amsterdam ; Boston : Morgan Kaufmann, ©2008 9780123705228 0123705223 (DLC) 2007029773 (OCoLC)157023025 Morgan Kaufmann series in systems on silicon. http://id.loc.gov/authorities/names/n2001146727 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=214763 Volltext FWS01 ZDB-4-EBA FWS_PDA_EBA https://www.sciencedirect.com/science/book/9780123705228 Volltext |
| spellingShingle | Reconfigurable computing : the theory and practice of FPGA-based computation / Morgan Kaufmann series in systems on silicon. Contents -- Preface -- Introduction -- Part One: Hardware -- Part I INTRO -- Chapter 1 -- General-Purpose FPGA Architecture -- Chapter 2 -- Reconfigurable Computing Devices -- Chapter 3 -- Reconfigurable Computing Systems -- Chapter 4 -- Reconfiguration Management -- Part Two: Software -- Part II Intro -- Chapter 5 -- Computer Models and System Architectures -- Andř DeHon Chapter 6 -- Hardware Description Languages (VHDL) -- Chapter 7 -- Compilation for Reconfigurable Computing Machines -- Chapter 8 -- Streaming Models -- 8.1 MATLAB/SIMULINK -- 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 -- OS/Runtime Systems -- Chapter 11 -- JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 -- Placement -- 13.1 General-purpose / FPGA -- 13.2 Datapath -- 13.3 Constructive -- Chapter 14 -- Routing -- Chapter 15 -- Retimin -- Chapter 16 -- Bitstream Generation, JBits -- Chapter 17 -- Fast Mapping -- Part Three: Application Development -- PART III INTRO -- Chapter 18 -- Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 -- Precision Analysis & Floating Point -- Chapter 21 -- Distributed Arithmetic -- Chapter 22 -- CORDIC -- Chapter 23 -- Task allocation: FPGA vs. CPU partitioning -- Part Four: Case Studies -- PART IV INTRO -- Chapter 24 -- Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 -- Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 -- Problem-specific circuitry: SAT Solving -- Chapter 27 -- Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 -- FDTD -- Chapter 30 -- Genetic Evolution -- Chapter 31 -- Packet Filtering (Networking application) -- Chapter 32 -- Active Pages [Memory centric] -- Part Five: Theoretical Underpinnings and Future Directions -- PART V INTRO -- Chapter 33- Theoretical Underpinnings, Metrics and Analysis -- Chapter 34 -- Defect and Fault Tolerance -- Chapter 35 -- Reconfigurable Computing and Nanotechnology. Adaptive computing systems. http://id.loc.gov/authorities/subjects/sh2002012109 Field programmable gate arrays. http://id.loc.gov/authorities/subjects/sh93009062 Systèmes adaptatifs (Informatique) Réseaux logiques programmables par l'utilisateur. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Adaptive computing systems fast Field programmable gate arrays fast Computerarchitektur gnd http://d-nb.info/gnd/4048717-9 Field programmable gate array gnd http://d-nb.info/gnd/4347749-5 Rekonfiguration gnd http://d-nb.info/gnd/4306238-6 |
| subject_GND | http://id.loc.gov/authorities/subjects/sh2002012109 http://id.loc.gov/authorities/subjects/sh93009062 http://d-nb.info/gnd/4048717-9 http://d-nb.info/gnd/4347749-5 http://d-nb.info/gnd/4306238-6 http://id.loc.gov/authorities/genreForms/gf2014026039 |
| title | Reconfigurable computing : the theory and practice of FPGA-based computation / |
| title_auth | Reconfigurable computing : the theory and practice of FPGA-based computation / |
| title_exact_search | Reconfigurable computing : the theory and practice of FPGA-based computation / |
| title_full | Reconfigurable computing : the theory and practice of FPGA-based computation / edited by Scott Hauck and André DeHon. |
| title_fullStr | Reconfigurable computing : the theory and practice of FPGA-based computation / edited by Scott Hauck and André DeHon. |
| title_full_unstemmed | Reconfigurable computing : the theory and practice of FPGA-based computation / edited by Scott Hauck and André DeHon. |
| title_short | Reconfigurable computing : |
| title_sort | reconfigurable computing the theory and practice of fpga based computation |
| title_sub | the theory and practice of FPGA-based computation / |
| topic | Adaptive computing systems. http://id.loc.gov/authorities/subjects/sh2002012109 Field programmable gate arrays. http://id.loc.gov/authorities/subjects/sh93009062 Systèmes adaptatifs (Informatique) Réseaux logiques programmables par l'utilisateur. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Adaptive computing systems fast Field programmable gate arrays fast Computerarchitektur gnd http://d-nb.info/gnd/4048717-9 Field programmable gate array gnd http://d-nb.info/gnd/4347749-5 Rekonfiguration gnd http://d-nb.info/gnd/4306238-6 |
| topic_facet | Adaptive computing systems. Field programmable gate arrays. Systèmes adaptatifs (Informatique) Réseaux logiques programmables par l'utilisateur. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. TECHNOLOGY & ENGINEERING Electronics Circuits Logic. COMPUTERS Logic Design. Adaptive computing systems Field programmable gate arrays Computerarchitektur Field programmable gate array Rekonfiguration Aufsatzsammlung. dissertations. Academic theses Academic theses. Thèses et écrits académiques. |
| url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=214763 https://www.sciencedirect.com/science/book/9780123705228 |
| work_keys_str_mv | AT hauckscott reconfigurablecomputingthetheoryandpracticeoffpgabasedcomputation AT dehonandre reconfigurablecomputingthetheoryandpracticeoffpgabasedcomputation |