Logic-timing simulation and the degradation delay model /:
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest...
Gespeichert in:
| 1. Verfasser: | |
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| Weitere Verfasser: | , |
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
London :
Imperial College Press,
©2006.
|
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Zusammenfassung: | This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the appl |
| Beschreibung: | 1 online resource (xvii, 267 pages) : illustrations |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 1860945899 9781860945892 1860947360 9781860947360 |
Internformat
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| 245 | 1 | 0 | |a Logic-timing simulation and the degradation delay model / |c Manuel J. Bellido, Jorge Juan, Manuel Valencia. |
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| 505 | 0 | 0 | |g Machine generated contents note: |g 1. |t Fundamentals of timing simulation -- |g 2. |t Delay models : evolution and trends -- |g 3. |t Degradation and inertial effects -- |g 4. |t CMOS inverter degradation delay model -- |g 5. |t Gate-level DDM -- |g 6. |t Logic level simulator design and implementation -- |g 7. |t DDM simulation results. |
| 520 | |a This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the appl | ||
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Datensatz im Suchindex
| DE-BY-FWS_katkey | ZDB-4-EBA-ocn191818232 |
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| _version_ | 1816881660498542592 |
| adam_text | |
| any_adam_object | |
| author | Bellido, Manuel J., 1964- |
| author2 | Juan Chico, Jorge Valencia, Manuel |
| author2_role | |
| author2_variant | c j j cj cjj m v mv |
| author_GND | http://id.loc.gov/authorities/names/n2002159270 |
| author_facet | Bellido, Manuel J., 1964- Juan Chico, Jorge Valencia, Manuel |
| author_role | |
| author_sort | Bellido, Manuel J., 1964- |
| author_variant | m j b mj mjb |
| building | Verbundindex |
| bvnumber | localFWS |
| callnumber-first | T - Technology |
| callnumber-label | TK7868 |
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| callnumber-search | TK7868.T5 B45 2006eb |
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| callnumber-subject | TK - Electrical and Nuclear Engineering |
| collection | ZDB-4-EBA |
| contents | Fundamentals of timing simulation -- Delay models : evolution and trends -- Degradation and inertial effects -- CMOS inverter degradation delay model -- Gate-level DDM -- Logic level simulator design and implementation -- DDM simulation results. |
| ctrlnum | (OCoLC)191818232 |
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| dewey-ones | 003 - Systems |
| dewey-raw | 003.3 |
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| discipline | Informatik |
| format | Electronic eBook |
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| indexdate | 2024-11-27T13:16:15Z |
| institution | BVB |
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| language | English |
| oclc_num | 191818232 |
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| publisher | Imperial College Press, |
| record_format | marc |
| spelling | Bellido, Manuel J., 1964- https://id.oclc.org/worldcat/entity/E39PCjqHfxXFrDQtPVvdcGcyr3 http://id.loc.gov/authorities/names/n2002159270 Logic-timing simulation and the degradation delay model / Manuel J. Bellido, Jorge Juan, Manuel Valencia. London : Imperial College Press, ©2006. 1 online resource (xvii, 267 pages) : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier data file Includes bibliographical references and index. Print version record. Machine generated contents note: 1. Fundamentals of timing simulation -- 2. Delay models : evolution and trends -- 3. Degradation and inertial effects -- 4. CMOS inverter degradation delay model -- 5. Gate-level DDM -- 6. Logic level simulator design and implementation -- 7. DDM simulation results. This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the appl Computer simulation. http://id.loc.gov/authorities/subjects/sh85029533 Mathematical models. http://id.loc.gov/authorities/subjects/sh85082124 Computer Simulation https://id.nlm.nih.gov/mesh/D003198 Models, Theoretical https://id.nlm.nih.gov/mesh/D008962 Simulation par ordinateur. Modèles mathématiques. simulation. aat mathematical models. aat COMPUTERS Computer Simulation. bisacsh Computer simulation fast Mathematical models fast Juan Chico, Jorge. Valencia, Manuel. has work: Logic-timing simulation and the degradation delay model (Text) https://id.oclc.org/worldcat/entity/E39PCGwJPpfwcqTK7hJPKWyHP3 https://id.oclc.org/worldcat/ontology/hasWork Print version: Bellido, Manuel J., 1964- Logic-timing simulation and the degradation delay model. London : Imperial College Press, ©2006 1860945899 (OCoLC)64790367 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=174630 Volltext |
| spellingShingle | Bellido, Manuel J., 1964- Logic-timing simulation and the degradation delay model / Fundamentals of timing simulation -- Delay models : evolution and trends -- Degradation and inertial effects -- CMOS inverter degradation delay model -- Gate-level DDM -- Logic level simulator design and implementation -- DDM simulation results. Computer simulation. http://id.loc.gov/authorities/subjects/sh85029533 Mathematical models. http://id.loc.gov/authorities/subjects/sh85082124 Computer Simulation https://id.nlm.nih.gov/mesh/D003198 Models, Theoretical https://id.nlm.nih.gov/mesh/D008962 Simulation par ordinateur. Modèles mathématiques. simulation. aat mathematical models. aat COMPUTERS Computer Simulation. bisacsh Computer simulation fast Mathematical models fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh85029533 http://id.loc.gov/authorities/subjects/sh85082124 https://id.nlm.nih.gov/mesh/D003198 https://id.nlm.nih.gov/mesh/D008962 |
| title | Logic-timing simulation and the degradation delay model / |
| title_alt | Fundamentals of timing simulation -- Delay models : evolution and trends -- Degradation and inertial effects -- CMOS inverter degradation delay model -- Gate-level DDM -- Logic level simulator design and implementation -- DDM simulation results. |
| title_auth | Logic-timing simulation and the degradation delay model / |
| title_exact_search | Logic-timing simulation and the degradation delay model / |
| title_full | Logic-timing simulation and the degradation delay model / Manuel J. Bellido, Jorge Juan, Manuel Valencia. |
| title_fullStr | Logic-timing simulation and the degradation delay model / Manuel J. Bellido, Jorge Juan, Manuel Valencia. |
| title_full_unstemmed | Logic-timing simulation and the degradation delay model / Manuel J. Bellido, Jorge Juan, Manuel Valencia. |
| title_short | Logic-timing simulation and the degradation delay model / |
| title_sort | logic timing simulation and the degradation delay model |
| topic | Computer simulation. http://id.loc.gov/authorities/subjects/sh85029533 Mathematical models. http://id.loc.gov/authorities/subjects/sh85082124 Computer Simulation https://id.nlm.nih.gov/mesh/D003198 Models, Theoretical https://id.nlm.nih.gov/mesh/D008962 Simulation par ordinateur. Modèles mathématiques. simulation. aat mathematical models. aat COMPUTERS Computer Simulation. bisacsh Computer simulation fast Mathematical models fast |
| topic_facet | Computer simulation. Mathematical models. Computer Simulation Models, Theoretical Simulation par ordinateur. Modèles mathématiques. simulation. mathematical models. COMPUTERS Computer Simulation. Computer simulation Mathematical models |
| url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=174630 |
| work_keys_str_mv | AT bellidomanuelj logictimingsimulationandthedegradationdelaymodel AT juanchicojorge logictimingsimulationandthedegradationdelaymodel AT valenciamanuel logictimingsimulationandthedegradationdelaymodel |