Formal verification: an essential toolkit for modern VLSI design
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| Main Authors: | , , |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Cambridge, MA, United States
Morgan Kaufmann Publishers, an imprint of Elsevier
[2023]
|
| Edition: | Second edition |
| Subjects: | |
| Online Access: | DE-91 |
| Physical Description: | 1 Online-Ressource (xix, 405 Seiten) Illustrationen |
| ISBN: | 9780323956130 |
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| illustrated | Illustrated |
| index_date | 2024-07-03T23:10:36Z |
| indexdate | 2025-03-05T05:00:27Z |
| institution | BVB |
| isbn | 9780323956130 |
| language | English |
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| physical | 1 Online-Ressource (xix, 405 Seiten) Illustrationen |
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| publisher | Morgan Kaufmann Publishers, an imprint of Elsevier |
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| spelling | Seligman, Erik Verfasser (DE-588)1102203785 aut Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar Second edition Cambridge, MA, United States Morgan Kaufmann Publishers, an imprint of Elsevier [2023] © 2023 1 Online-Ressource (xix, 405 Seiten) Illustrationen txt rdacontent c rdamedia cr rdacarrier Electronic circuits-Testing Integrated circuits-Very large scale integration-Design and construction Verilog (Computer hardware description language) Schubert, Tom Verfasser aut Kumar, M. V. Achutha Kiran Verfasser aut Erscheint auch als Seligman, Erik Formal Verification San Diego : Elsevier Science & Technology,c2023 Druck-Ausgabe 978-0-323-95612-3 |
| spellingShingle | Seligman, Erik Schubert, Tom Kumar, M. V. Achutha Kiran Formal verification an essential toolkit for modern VLSI design Electronic circuits-Testing Integrated circuits-Very large scale integration-Design and construction Verilog (Computer hardware description language) |
| title | Formal verification an essential toolkit for modern VLSI design |
| title_auth | Formal verification an essential toolkit for modern VLSI design |
| title_exact_search | Formal verification an essential toolkit for modern VLSI design |
| title_exact_search_txtP | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_full | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar |
| title_fullStr | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar |
| title_full_unstemmed | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar |
| title_short | Formal verification |
| title_sort | formal verification an essential toolkit for modern vlsi design |
| title_sub | an essential toolkit for modern VLSI design |
| topic | Electronic circuits-Testing Integrated circuits-Very large scale integration-Design and construction Verilog (Computer hardware description language) |
| topic_facet | Electronic circuits-Testing Integrated circuits-Very large scale integration-Design and construction Verilog (Computer hardware description language) |
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