APA (7th ed.) Citation

Barkalov, A., Titarenko, L., Mielcarek, K., Mazurkiewicz, M., & Kawecka, E. (2022). Logic Synthesis for VLSI-Based Combined Finite State Machines: Synthesis Targeting ASICs, CPLDs and FPGAs (1st ed. 2022.). Springer International Publishing. https://doi.org/10.1007/978-3-031-16027-1

Chicago Style (17th ed.) Citation

Barkalov, Alexander, Larysa Titarenko, Kamil Mielcarek, Małgorzata Mazurkiewicz, and Elżbieta Kawecka. Logic Synthesis for VLSI-Based Combined Finite State Machines: Synthesis Targeting ASICs, CPLDs and FPGAs. 1st ed. 2022. Cham: Springer International Publishing, 2022. https://doi.org/10.1007/978-3-031-16027-1.

MLA (9th ed.) Citation

Barkalov, Alexander, et al. Logic Synthesis for VLSI-Based Combined Finite State Machines: Synthesis Targeting ASICs, CPLDs and FPGAs. 1st ed. 2022. Springer International Publishing, 2022. https://doi.org/10.1007/978-3-031-16027-1.