Network-on-chip: the next generation of system-on-chip integration
Addresses the Challenges Associated with System-on-Chip IntegrationNetwork-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with...
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| Main Authors: | , |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boca Raton, FL
CRC Press, Taylor & Francis Group
[2015]
|
| Subjects: | |
| Online Access: | Volltext |
| Summary: | Addresses the Challenges Associated with System-on-Chip IntegrationNetwork-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design |
| Physical Description: | 1 Online-Ressource (xvii, 369 Seiten) illustrations |
| ISBN: | 1315216078 1322629250 1351823272 1466565268 1466565276 9781315216072 9781322629254 9781351823272 9781466565265 9781466565272 |
| Access: | Open Access |
Staff View
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| 505 | 8 | |a 1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends | |
| 506 | 0 | |a Open Access |5 EbpS | |
| 520 | 3 | |a Addresses the Challenges Associated with System-on-Chip IntegrationNetwork-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design | |
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| author | Kundu, Santanu Chattopadhyay, Santanu |
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| contents | 1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends |
| ctrlnum | (OCoLC)895661009 (DE-599)BVBBV048282969 |
| format | Electronic eBook |
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| id | DE-604.BV048282969 |
| illustrated | Illustrated |
| index_date | 2024-07-03T20:00:58Z |
| indexdate | 2024-07-10T09:34:06Z |
| institution | BVB |
| isbn | 1315216078 1322629250 1351823272 1466565268 1466565276 9781315216072 9781322629254 9781351823272 9781466565265 9781466565272 |
| language | English |
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| physical | 1 Online-Ressource (xvii, 369 Seiten) illustrations |
| psigel | ZDB-4-EOAC |
| publishDate | 2015 |
| publishDateSearch | 2015 |
| publishDateSort | 2015 |
| publisher | CRC Press, Taylor & Francis Group |
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| spelling | Kundu, Santanu Verfasser aut Network-on-chip the next generation of system-on-chip integration Santanu Kundu, Santanu Chattopadhyay Boca Raton, FL CRC Press, Taylor & Francis Group [2015] ©2015 1 Online-Ressource (xvii, 369 Seiten) illustrations txt rdacontent c rdamedia cr rdacarrier 1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends Open Access EbpS Addresses the Challenges Associated with System-on-Chip IntegrationNetwork-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design English Réseaux sur puce Networks on a chip TECHNOLOGY & ENGINEERING Mechanical Electronic books Chattopadhyay, Santanu author oth Erscheint auch als Druck-Ausgabe Kundu, Santanu Network-on-chip Boca Raton, FL : CRC Press : Taylor & Francis Group, 2015 9781466565265 https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=906066 Verlag kostenfrei Volltext data file |
| spellingShingle | Kundu, Santanu Chattopadhyay, Santanu Network-on-chip the next generation of system-on-chip integration 1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends Réseaux sur puce Networks on a chip TECHNOLOGY & ENGINEERING Mechanical |
| title | Network-on-chip the next generation of system-on-chip integration |
| title_auth | Network-on-chip the next generation of system-on-chip integration |
| title_exact_search | Network-on-chip the next generation of system-on-chip integration |
| title_exact_search_txtP | Network-on-chip the next generation of system-on-chip integration |
| title_full | Network-on-chip the next generation of system-on-chip integration Santanu Kundu, Santanu Chattopadhyay |
| title_fullStr | Network-on-chip the next generation of system-on-chip integration Santanu Kundu, Santanu Chattopadhyay |
| title_full_unstemmed | Network-on-chip the next generation of system-on-chip integration Santanu Kundu, Santanu Chattopadhyay |
| title_short | Network-on-chip |
| title_sort | network on chip the next generation of system on chip integration |
| title_sub | the next generation of system-on-chip integration |
| topic | Réseaux sur puce Networks on a chip TECHNOLOGY & ENGINEERING Mechanical |
| topic_facet | Réseaux sur puce Networks on a chip TECHNOLOGY & ENGINEERING |
| url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=906066 |
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