Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces: high performance compute and system-in-package
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| Other Authors: | , |
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| Format: | Electronic eBook |
| Language: | English |
| Published: |
Hoboken, New Jersey
Wiley
[2022]
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| Subjects: | |
| Online Access: | FHI01 TUM01 |
| Item Description: | Description based on publisher supplied metadata and other sources |
| Physical Description: | 1 Online-Ressource (xv, 296 Seiten) Illustrationen, Diagramme |
| ISBN: | 9781119793847 9781119793892 9781119793908 |
Staff View
MARC
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| 245 | 1 | 0 | |a Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces |b high performance compute and system-in-package |c edited by Beth Keser, Steffen Kröhnert |
| 264 | 1 | |a Hoboken, New Jersey |b Wiley |c [2022] | |
| 264 | 4 | |c © 2022 | |
| 300 | |a 1 Online-Ressource (xv, 296 Seiten) |b Illustrationen, Diagramme | ||
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| 500 | |a Description based on publisher supplied metadata and other sources | ||
| 505 | 8 | |a Cover -- Title Page -- Copyright -- Contents -- Preface -- Chapter 1 Fan-Out Wafer and Panel Level Packaging Market and Technology Trends -- 1.1 Introduction to Fan-Out Packaging -- 1.1.1 Historical Perspective -- 1.1.2 Key Drivers: Why Fan-Out Packaging? -- 1.1.3 FO-WLP vs. FO-PLP -- 1.1.4 Future of Fan-Out Packaging for Heterogeneous Integration -- 1.2 Market Overview and Applications -- 1.2.1 Fan-Out Packaging Definition -- 1.2.2 Market Segmentation: Core FO vs. HD FO vs. UHD FO -- 1.2.3 Market Valuation: Forecast of Revenue and Volume -- 1.2.4 Current and Future Target Markets -- 1.2.5 Applications of Fan-Out Packaging -- 1.3 Technology Trends and Supply Chain -- 1.3.1 Fan-Out Packaging Technology Roadmaps -- 1.3.2 Fan-Out Packaging Technology by Manufacturer -- 1.3.2.1 Amkor -- 1.3.2.2 JCET -- 1.3.2.3 NXP -- 1.3.2.4 DECA Technologies -- 1.3.2.5 ASE -- 1.3.2.6 TSMC -- 1.3.2.7 PTI -- 1.3.2.8 Samsung Electronics -- 1.3.2.9 Huatian -- 1.3.3 Supply Chain Overview -- 1.3.4 Analysis of the Latest Developments in the Supply Chain -- 1.4 Fan-Out Panel-Level Packaging (FO-PLP) -- 1.4.1 Motivation and Challenges for FO-PLP -- 1.4.2 FO-PLP Market and Applications -- 1.4.3 FO-PLP Supplier Overview -- 1.5 System Device Teardowns -- 1.5.1 Teardown of End-Systems with Fan-Out Packaging -- 1.5.2 Technology Comparison -- 1.5.2.1 Radar IC: eWLB vs. RCP -- 1.5.2.2 MCM/SiP: RCP-SiP vs. eWLB -- 1.5.2.3 PMIC: eWLB vs. M-Series -- 1.5.3 Cost Comparison -- 1.6 Conclusion -- References -- Chapter 2 Cost Comparison of FO-WLP with Other Technologies -- 2.1 Introduction -- 2.2 Activity-Based Cost Modeling -- 2.3 Cost Analysis of FO-WLP Variations -- 2.3.1 Process Segment Costs -- 2.3.1.1 Die Preparation -- 2.3.1.2 Carrier -- 2.3.1.3 Die Bond -- 2.3.1.4 Mold -- 2.3.1.5 Backgrinding -- 2.3.1.6 RDL -- 2.3.1.7 UBM -- 2.3.1.8 Flux and Ball Attach -- 2.3.1.9 Singulation | |
| 505 | 8 | |a 2.3.2 FO-WLP Variations -- 2.3.2.1 Carrier -- 2.3.2.2 Die Cost and Preparation -- 2.3.2.3 Die Bond -- 2.3.2.4 Mold/Mold + CUF -- 2.3.2.5 Backgrind/Post-mold Grind -- 2.3.2.6 Scrap -- 2.4 Cost of FO-WLP versus Wire Bond and Flip Chip -- 2.5 Package-on-Package Cost Analysis -- 2.6 Conclusions -- References -- Chapter 3 Integrated Fan-Out (InFO) for Mobile Computing -- 3.1 Introduction -- 3.2 Fan-In Wafer-Level Packaging -- 3.2.1 Dielectric and Redistribution Layers (RDL) -- 3.2.2 Under Bump Metallization (UBM) -- 3.2.3 Reliability and Challenges -- 3.2.4 Large Die WLP -- 3.3 Fan-Out Wafer-Level System Integration -- 3.3.1 Chip-First vs. Chip-Last -- 3.3.2 Molding and Planarization -- 3.3.3 Redistribution Layer (RDL) -- 3.3.4 Through Via and Vertical Interconnection -- 3.4 Integrated Passive Devices (IPDs) -- 3.4.1 High Q-Factor 3D Solenoid Inductor -- 3.4.2 Antenna in Package (AiP) and 5G Communication -- 3.4.3 Passive Devices for Millimeter Wave System Integration -- 3.5 Power, Performance, Form Factor, and Cost -- 3.5.1 Signal and Power Integrity -- 3.5.2 Heat Dissipation and Thermal Performance -- 3.5.3 Form Factor and Thickness -- 3.5.4 Cycle Time to Market and Cost -- 3.6 Summary -- References -- Chapter 4 Integrated Fan-Out (InFO) for High Performance Computing -- 4.1 Introduction -- 4.2 3DFabric and System-on-Integrated-Chip (SoIC) -- 4.3 CoWoS-R, CoWoS-S, and CoWoS-L -- 4.4 InFO-L and InFO-R -- 4.5 Info Ultra-High-Density Interconnect (InFO-UHD) -- 4.6 Multi-Stack System Integration (MUST) and Must-in-Must (MiM) -- 4.7 InFO on Substate (InFO-oS) and InFO Local Silicon Interconnect (InFO-L) -- 4.8 InFO with Memory on Substrate (InFO-MS) -- 4.9 InFO 3D Multi-Silicon (InFO-3DMS) and CoWoS-L -- 4.10 InFO System on Wafer (InFO& -- uscore -- SoW) -- 4.11 System on Integrated Substrate (SoIS) -- 4.12 Immersion Memory Compute (ImMC) -- 4.13 Summary | |
| 505 | 8 | |a References -- Chapter 5 Adaptive Patterning and M-Series for High Density Integration -- 5.1 Technology Description -- 5.2 Applications and Markets -- 5.3 Basic Package Construction -- 5.4 Manufacturing Process Flow and BOM -- 5.5 Design Features and System Integration Capability -- 5.6 Adaptive Patterning -- 5.7 Manufacturing Format and Scalability -- 5.8 Package Performance -- 5.9 Robustness and Reliability Data -- 5.10 Electrical Test Considerations -- 5.11 Summary -- References -- Chapter 6 Panel-Level Packaging for Heterogenous Integration -- 6.1 Introduction -- 6.2 Fan-Out Panel-Level Packaging -- 6.3 Economic Efficiency Analysis of PLP -- 6.4 Summary -- References -- Chapter 7 Next Generation Chip Embedding Technology for High Efficiency Power Modules and Power SiPs -- 7.1 Technology Description -- 7.2 Basic Package Construction -- 7.3 Applications and Markets (HPC, SiP) -- 7.4 Manufacturing Process Flow and BOM -- 7.5 Design Features -- 7.6 System Integration Capability -- 7.7 Package Performance -- 7.8 Robustness and Reliability Data -- 7.9 Electrical Test Considerations -- 7.10 Summary -- References -- Chapter 8 Die Integration Technologies on Advanced Substrates Including Embedding and Cavities -- 8.1 Introduction -- 8.2 Heterogeneous Integration by Use of Embedded Chip Packaging (ECP) -- 8.3 Embedding Process -- 8.4 Component Selection -- 8.5 Design Technology -- 8.6 Testing -- 8.7 Applications for ECP Technology -- 8.8 Heterogeneous Integration Using Cavities in PCB -- 8.9 Package Performance, Robustness, and Reliability -- 8.10 Conclusion -- References -- Chapter 9 Advanced Embedded Trace Substrate - A Flexible Alternative to Fan-Out Wafer Level Packaging -- 9.1 Technology Description -- 9.1.1 C2iM Technology -- 9.1.2 C2iM-PLP Technology -- 9.2 Applications and Markets -- 9.3 Basic Package Construction -- 9.3.1 C2iM-PLP Experience | |
| 505 | 8 | |a 9.3.2 C2iM-PLP Advantages and Disadvantages Compared to Wirebond Quad Flat No Lead (WB-QFN) and Flip-Chip QFN (FC-QFN) Packages -- 9.3.3 C2iM-PLP Advantages and Disadvantages Compared to WLP and FO-WLP -- 9.3.4 Future Applications -- 9.3.5 Limitations of C2iM-PLP -- 9.4 Manufacturing Process Flow and BOM -- 9.5 Design Features -- 9.5.1 Package Design Rules -- 9.5.2 Design Rules for Die UBM -- 9.5.3 Design Rules for Die Side by Side -- 9.5.4 Design Rules for Cu Pillar -- 9.6 System Integration Capability -- 9.7 Manufacturing Format and Scalability -- 9.8 Package Performance -- 9.8.1 Electrical Performance -- 9.8.2 Thermal Performance -- 9.9 Robustness and Reliability Data -- 9.9.1 Automotive Reliability Certification Pass -- 9.9.2 Board Level Reliability Verification Pass -- 9.10 Electrical Test Considerations -- 9.11 Summary -- References -- Chapter 10 Flexible Hybrid Electronics Using Fan-Out Wafer-Level Packaging -- 10.1 Introduction -- 10.2 Recent Trends in Packaging -- 10.3 FHE Using FO-WLP - FlexTrate -- 10.4 Applications on FlexTrate -- Acknowledgments -- References -- Chapter 11 Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations -- 11.1 Introduction -- 11.2 Heterogeneous Interconnect Stitching Technology (HIST) -- 11.3 Thermal Evaluation of 2.5D Integration Using Bridge-Chip Technology -- 11.3.1 2.5D and 3D Benchmark Architectures -- 11.3.1.1 2.5D Integration -- 11.3.1.2 3D Integration -- 11.3.2 Thermal Modeling and Specifications -- 11.3.3 Comparison of Different 2.5D Integration Schemes -- 11.3.4 Thermal Comparison between 2.5D and 3D Integration -- 11.3.5 Thermal Study of Bridge-Chip 2.5D Integration -- 11.3.5.1 Impact of TIM conductivity -- 11.3.5.2 Die Thickness -- 11.3.5.3 Die Spacing -- 11.3.6 Polylithic 3D Integration | |
| 505 | 8 | |a 11.4 Monolithic Microfluidic Cooling of High-Power Electronics -- 11.4.1 Experimental Demonstration and Characterization on Single Die Systems -- 11.4.2 Microfluidic Cooling of 2.5D Devices: Experimental Demonstration -- 11.4.3 Monolithic Microfluidic Cooling of 3D Integration: Modelling Electrical Implications for I/Os -- 11.5 Conclusion -- Acknowledgments -- References -- Index -- EULA. | |
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| contents | Cover -- Title Page -- Copyright -- Contents -- Preface -- Chapter 1 Fan-Out Wafer and Panel Level Packaging Market and Technology Trends -- 1.1 Introduction to Fan-Out Packaging -- 1.1.1 Historical Perspective -- 1.1.2 Key Drivers: Why Fan-Out Packaging? -- 1.1.3 FO-WLP vs. FO-PLP -- 1.1.4 Future of Fan-Out Packaging for Heterogeneous Integration -- 1.2 Market Overview and Applications -- 1.2.1 Fan-Out Packaging Definition -- 1.2.2 Market Segmentation: Core FO vs. HD FO vs. UHD FO -- 1.2.3 Market Valuation: Forecast of Revenue and Volume -- 1.2.4 Current and Future Target Markets -- 1.2.5 Applications of Fan-Out Packaging -- 1.3 Technology Trends and Supply Chain -- 1.3.1 Fan-Out Packaging Technology Roadmaps -- 1.3.2 Fan-Out Packaging Technology by Manufacturer -- 1.3.2.1 Amkor -- 1.3.2.2 JCET -- 1.3.2.3 NXP -- 1.3.2.4 DECA Technologies -- 1.3.2.5 ASE -- 1.3.2.6 TSMC -- 1.3.2.7 PTI -- 1.3.2.8 Samsung Electronics -- 1.3.2.9 Huatian -- 1.3.3 Supply Chain Overview -- 1.3.4 Analysis of the Latest Developments in the Supply Chain -- 1.4 Fan-Out Panel-Level Packaging (FO-PLP) -- 1.4.1 Motivation and Challenges for FO-PLP -- 1.4.2 FO-PLP Market and Applications -- 1.4.3 FO-PLP Supplier Overview -- 1.5 System Device Teardowns -- 1.5.1 Teardown of End-Systems with Fan-Out Packaging -- 1.5.2 Technology Comparison -- 1.5.2.1 Radar IC: eWLB vs. RCP -- 1.5.2.2 MCM/SiP: RCP-SiP vs. eWLB -- 1.5.2.3 PMIC: eWLB vs. M-Series -- 1.5.3 Cost Comparison -- 1.6 Conclusion -- References -- Chapter 2 Cost Comparison of FO-WLP with Other Technologies -- 2.1 Introduction -- 2.2 Activity-Based Cost Modeling -- 2.3 Cost Analysis of FO-WLP Variations -- 2.3.1 Process Segment Costs -- 2.3.1.1 Die Preparation -- 2.3.1.2 Carrier -- 2.3.1.3 Die Bond -- 2.3.1.4 Mold -- 2.3.1.5 Backgrinding -- 2.3.1.6 RDL -- 2.3.1.7 UBM -- 2.3.1.8 Flux and Ball Attach -- 2.3.1.9 Singulation 2.3.2 FO-WLP Variations -- 2.3.2.1 Carrier -- 2.3.2.2 Die Cost and Preparation -- 2.3.2.3 Die Bond -- 2.3.2.4 Mold/Mold + CUF -- 2.3.2.5 Backgrind/Post-mold Grind -- 2.3.2.6 Scrap -- 2.4 Cost of FO-WLP versus Wire Bond and Flip Chip -- 2.5 Package-on-Package Cost Analysis -- 2.6 Conclusions -- References -- Chapter 3 Integrated Fan-Out (InFO) for Mobile Computing -- 3.1 Introduction -- 3.2 Fan-In Wafer-Level Packaging -- 3.2.1 Dielectric and Redistribution Layers (RDL) -- 3.2.2 Under Bump Metallization (UBM) -- 3.2.3 Reliability and Challenges -- 3.2.4 Large Die WLP -- 3.3 Fan-Out Wafer-Level System Integration -- 3.3.1 Chip-First vs. Chip-Last -- 3.3.2 Molding and Planarization -- 3.3.3 Redistribution Layer (RDL) -- 3.3.4 Through Via and Vertical Interconnection -- 3.4 Integrated Passive Devices (IPDs) -- 3.4.1 High Q-Factor 3D Solenoid Inductor -- 3.4.2 Antenna in Package (AiP) and 5G Communication -- 3.4.3 Passive Devices for Millimeter Wave System Integration -- 3.5 Power, Performance, Form Factor, and Cost -- 3.5.1 Signal and Power Integrity -- 3.5.2 Heat Dissipation and Thermal Performance -- 3.5.3 Form Factor and Thickness -- 3.5.4 Cycle Time to Market and Cost -- 3.6 Summary -- References -- Chapter 4 Integrated Fan-Out (InFO) for High Performance Computing -- 4.1 Introduction -- 4.2 3DFabric and System-on-Integrated-Chip (SoIC) -- 4.3 CoWoS-R, CoWoS-S, and CoWoS-L -- 4.4 InFO-L and InFO-R -- 4.5 Info Ultra-High-Density Interconnect (InFO-UHD) -- 4.6 Multi-Stack System Integration (MUST) and Must-in-Must (MiM) -- 4.7 InFO on Substate (InFO-oS) and InFO Local Silicon Interconnect (InFO-L) -- 4.8 InFO with Memory on Substrate (InFO-MS) -- 4.9 InFO 3D Multi-Silicon (InFO-3DMS) and CoWoS-L -- 4.10 InFO System on Wafer (InFO& -- uscore -- SoW) -- 4.11 System on Integrated Substrate (SoIS) -- 4.12 Immersion Memory Compute (ImMC) -- 4.13 Summary References -- Chapter 5 Adaptive Patterning and M-Series for High Density Integration -- 5.1 Technology Description -- 5.2 Applications and Markets -- 5.3 Basic Package Construction -- 5.4 Manufacturing Process Flow and BOM -- 5.5 Design Features and System Integration Capability -- 5.6 Adaptive Patterning -- 5.7 Manufacturing Format and Scalability -- 5.8 Package Performance -- 5.9 Robustness and Reliability Data -- 5.10 Electrical Test Considerations -- 5.11 Summary -- References -- Chapter 6 Panel-Level Packaging for Heterogenous Integration -- 6.1 Introduction -- 6.2 Fan-Out Panel-Level Packaging -- 6.3 Economic Efficiency Analysis of PLP -- 6.4 Summary -- References -- Chapter 7 Next Generation Chip Embedding Technology for High Efficiency Power Modules and Power SiPs -- 7.1 Technology Description -- 7.2 Basic Package Construction -- 7.3 Applications and Markets (HPC, SiP) -- 7.4 Manufacturing Process Flow and BOM -- 7.5 Design Features -- 7.6 System Integration Capability -- 7.7 Package Performance -- 7.8 Robustness and Reliability Data -- 7.9 Electrical Test Considerations -- 7.10 Summary -- References -- Chapter 8 Die Integration Technologies on Advanced Substrates Including Embedding and Cavities -- 8.1 Introduction -- 8.2 Heterogeneous Integration by Use of Embedded Chip Packaging (ECP) -- 8.3 Embedding Process -- 8.4 Component Selection -- 8.5 Design Technology -- 8.6 Testing -- 8.7 Applications for ECP Technology -- 8.8 Heterogeneous Integration Using Cavities in PCB -- 8.9 Package Performance, Robustness, and Reliability -- 8.10 Conclusion -- References -- Chapter 9 Advanced Embedded Trace Substrate - A Flexible Alternative to Fan-Out Wafer Level Packaging -- 9.1 Technology Description -- 9.1.1 C2iM Technology -- 9.1.2 C2iM-PLP Technology -- 9.2 Applications and Markets -- 9.3 Basic Package Construction -- 9.3.1 C2iM-PLP Experience 9.3.2 C2iM-PLP Advantages and Disadvantages Compared to Wirebond Quad Flat No Lead (WB-QFN) and Flip-Chip QFN (FC-QFN) Packages -- 9.3.3 C2iM-PLP Advantages and Disadvantages Compared to WLP and FO-WLP -- 9.3.4 Future Applications -- 9.3.5 Limitations of C2iM-PLP -- 9.4 Manufacturing Process Flow and BOM -- 9.5 Design Features -- 9.5.1 Package Design Rules -- 9.5.2 Design Rules for Die UBM -- 9.5.3 Design Rules for Die Side by Side -- 9.5.4 Design Rules for Cu Pillar -- 9.6 System Integration Capability -- 9.7 Manufacturing Format and Scalability -- 9.8 Package Performance -- 9.8.1 Electrical Performance -- 9.8.2 Thermal Performance -- 9.9 Robustness and Reliability Data -- 9.9.1 Automotive Reliability Certification Pass -- 9.9.2 Board Level Reliability Verification Pass -- 9.10 Electrical Test Considerations -- 9.11 Summary -- References -- Chapter 10 Flexible Hybrid Electronics Using Fan-Out Wafer-Level Packaging -- 10.1 Introduction -- 10.2 Recent Trends in Packaging -- 10.3 FHE Using FO-WLP - FlexTrate -- 10.4 Applications on FlexTrate -- Acknowledgments -- References -- Chapter 11 Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations -- 11.1 Introduction -- 11.2 Heterogeneous Interconnect Stitching Technology (HIST) -- 11.3 Thermal Evaluation of 2.5D Integration Using Bridge-Chip Technology -- 11.3.1 2.5D and 3D Benchmark Architectures -- 11.3.1.1 2.5D Integration -- 11.3.1.2 3D Integration -- 11.3.2 Thermal Modeling and Specifications -- 11.3.3 Comparison of Different 2.5D Integration Schemes -- 11.3.4 Thermal Comparison between 2.5D and 3D Integration -- 11.3.5 Thermal Study of Bridge-Chip 2.5D Integration -- 11.3.5.1 Impact of TIM conductivity -- 11.3.5.2 Die Thickness -- 11.3.5.3 Die Spacing -- 11.3.6 Polylithic 3D Integration 11.4 Monolithic Microfluidic Cooling of High-Power Electronics -- 11.4.1 Experimental Demonstration and Characterization on Single Die Systems -- 11.4.2 Microfluidic Cooling of 2.5D Devices: Experimental Demonstration -- 11.4.3 Monolithic Microfluidic Cooling of 3D Integration: Modelling Electrical Implications for I/Os -- 11.5 Conclusion -- Acknowledgments -- References -- Index -- EULA. |
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| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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ind2=" "><subfield code="a">ELT 356</subfield><subfield code="2">stub</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces</subfield><subfield code="b">high performance compute and system-in-package</subfield><subfield code="c">edited by Beth Keser, Steffen Kröhnert</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken, New Jersey</subfield><subfield code="b">Wiley</subfield><subfield code="c">[2022]</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">© 2022</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (xv, 296 Seiten)</subfield><subfield code="b">Illustrationen, Diagramme</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Description based on publisher supplied metadata and other sources</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Cover -- Title Page -- Copyright -- Contents -- Preface -- Chapter 1 Fan-Out Wafer and Panel Level Packaging Market and Technology Trends -- 1.1 Introduction to Fan-Out Packaging -- 1.1.1 Historical Perspective -- 1.1.2 Key Drivers: Why Fan-Out Packaging? -- 1.1.3 FO-WLP vs. FO-PLP -- 1.1.4 Future of Fan-Out Packaging for Heterogeneous Integration -- 1.2 Market Overview and Applications -- 1.2.1 Fan-Out Packaging Definition -- 1.2.2 Market Segmentation: Core FO vs. HD FO vs. UHD FO -- 1.2.3 Market Valuation: Forecast of Revenue and Volume -- 1.2.4 Current and Future Target Markets -- 1.2.5 Applications of Fan-Out Packaging -- 1.3 Technology Trends and Supply Chain -- 1.3.1 Fan-Out Packaging Technology Roadmaps -- 1.3.2 Fan-Out Packaging Technology by Manufacturer -- 1.3.2.1 Amkor -- 1.3.2.2 JCET -- 1.3.2.3 NXP -- 1.3.2.4 DECA Technologies -- 1.3.2.5 ASE -- 1.3.2.6 TSMC -- 1.3.2.7 PTI -- 1.3.2.8 Samsung Electronics -- 1.3.2.9 Huatian -- 1.3.3 Supply Chain Overview -- 1.3.4 Analysis of the Latest Developments in the Supply Chain -- 1.4 Fan-Out Panel-Level Packaging (FO-PLP) -- 1.4.1 Motivation and Challenges for FO-PLP -- 1.4.2 FO-PLP Market and Applications -- 1.4.3 FO-PLP Supplier Overview -- 1.5 System Device Teardowns -- 1.5.1 Teardown of End-Systems with Fan-Out Packaging -- 1.5.2 Technology Comparison -- 1.5.2.1 Radar IC: eWLB vs. RCP -- 1.5.2.2 MCM/SiP: RCP-SiP vs. eWLB -- 1.5.2.3 PMIC: eWLB vs. M-Series -- 1.5.3 Cost Comparison -- 1.6 Conclusion -- References -- Chapter 2 Cost Comparison of FO-WLP with Other Technologies -- 2.1 Introduction -- 2.2 Activity-Based Cost Modeling -- 2.3 Cost Analysis of FO-WLP Variations -- 2.3.1 Process Segment Costs -- 2.3.1.1 Die Preparation -- 2.3.1.2 Carrier -- 2.3.1.3 Die Bond -- 2.3.1.4 Mold -- 2.3.1.5 Backgrinding -- 2.3.1.6 RDL -- 2.3.1.7 UBM -- 2.3.1.8 Flux and Ball Attach -- 2.3.1.9 Singulation</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">2.3.2 FO-WLP Variations -- 2.3.2.1 Carrier -- 2.3.2.2 Die Cost and Preparation -- 2.3.2.3 Die Bond -- 2.3.2.4 Mold/Mold + CUF -- 2.3.2.5 Backgrind/Post-mold Grind -- 2.3.2.6 Scrap -- 2.4 Cost of FO-WLP versus Wire Bond and Flip Chip -- 2.5 Package-on-Package Cost Analysis -- 2.6 Conclusions -- References -- Chapter 3 Integrated Fan-Out (InFO) for Mobile Computing -- 3.1 Introduction -- 3.2 Fan-In Wafer-Level Packaging -- 3.2.1 Dielectric and Redistribution Layers (RDL) -- 3.2.2 Under Bump Metallization (UBM) -- 3.2.3 Reliability and Challenges -- 3.2.4 Large Die WLP -- 3.3 Fan-Out Wafer-Level System Integration -- 3.3.1 Chip-First vs. Chip-Last -- 3.3.2 Molding and Planarization -- 3.3.3 Redistribution Layer (RDL) -- 3.3.4 Through Via and Vertical Interconnection -- 3.4 Integrated Passive Devices (IPDs) -- 3.4.1 High Q-Factor 3D Solenoid Inductor -- 3.4.2 Antenna in Package (AiP) and 5G Communication -- 3.4.3 Passive Devices for Millimeter Wave System Integration -- 3.5 Power, Performance, Form Factor, and Cost -- 3.5.1 Signal and Power Integrity -- 3.5.2 Heat Dissipation and Thermal Performance -- 3.5.3 Form Factor and Thickness -- 3.5.4 Cycle Time to Market and Cost -- 3.6 Summary -- References -- Chapter 4 Integrated Fan-Out (InFO) for High Performance Computing -- 4.1 Introduction -- 4.2 3DFabric and System-on-Integrated-Chip (SoIC) -- 4.3 CoWoS-R, CoWoS-S, and CoWoS-L -- 4.4 InFO-L and InFO-R -- 4.5 Info Ultra-High-Density Interconnect (InFO-UHD) -- 4.6 Multi-Stack System Integration (MUST) and Must-in-Must (MiM) -- 4.7 InFO on Substate (InFO-oS) and InFO Local Silicon Interconnect (InFO-L) -- 4.8 InFO with Memory on Substrate (InFO-MS) -- 4.9 InFO 3D Multi-Silicon (InFO-3DMS) and CoWoS-L -- 4.10 InFO System on Wafer (InFO&amp -- uscore -- SoW) -- 4.11 System on Integrated Substrate (SoIS) -- 4.12 Immersion Memory Compute (ImMC) -- 4.13 Summary</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">References -- Chapter 5 Adaptive Patterning and M-Series for High Density Integration -- 5.1 Technology Description -- 5.2 Applications and Markets -- 5.3 Basic Package Construction -- 5.4 Manufacturing Process Flow and BOM -- 5.5 Design Features and System Integration Capability -- 5.6 Adaptive Patterning -- 5.7 Manufacturing Format and Scalability -- 5.8 Package Performance -- 5.9 Robustness and Reliability Data -- 5.10 Electrical Test Considerations -- 5.11 Summary -- References -- Chapter 6 Panel-Level Packaging for Heterogenous Integration -- 6.1 Introduction -- 6.2 Fan-Out Panel-Level Packaging -- 6.3 Economic Efficiency Analysis of PLP -- 6.4 Summary -- References -- Chapter 7 Next Generation Chip Embedding Technology for High Efficiency Power Modules and Power SiPs -- 7.1 Technology Description -- 7.2 Basic Package Construction -- 7.3 Applications and Markets (HPC, SiP) -- 7.4 Manufacturing Process Flow and BOM -- 7.5 Design Features -- 7.6 System Integration Capability -- 7.7 Package Performance -- 7.8 Robustness and Reliability Data -- 7.9 Electrical Test Considerations -- 7.10 Summary -- References -- Chapter 8 Die Integration Technologies on Advanced Substrates Including Embedding and Cavities -- 8.1 Introduction -- 8.2 Heterogeneous Integration by Use of Embedded Chip Packaging (ECP) -- 8.3 Embedding Process -- 8.4 Component Selection -- 8.5 Design Technology -- 8.6 Testing -- 8.7 Applications for ECP Technology -- 8.8 Heterogeneous Integration Using Cavities in PCB -- 8.9 Package Performance, Robustness, and Reliability -- 8.10 Conclusion -- References -- Chapter 9 Advanced Embedded Trace Substrate - A Flexible Alternative to Fan-Out Wafer Level Packaging -- 9.1 Technology Description -- 9.1.1 C2iM Technology -- 9.1.2 C2iM-PLP Technology -- 9.2 Applications and Markets -- 9.3 Basic Package Construction -- 9.3.1 C2iM-PLP Experience</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">9.3.2 C2iM-PLP Advantages and Disadvantages Compared to Wirebond Quad Flat No Lead (WB-QFN) and Flip-Chip QFN (FC-QFN) Packages -- 9.3.3 C2iM-PLP Advantages and Disadvantages Compared to WLP and FO-WLP -- 9.3.4 Future Applications -- 9.3.5 Limitations of C2iM-PLP -- 9.4 Manufacturing Process Flow and BOM -- 9.5 Design Features -- 9.5.1 Package Design Rules -- 9.5.2 Design Rules for Die UBM -- 9.5.3 Design Rules for Die Side by Side -- 9.5.4 Design Rules for Cu Pillar -- 9.6 System Integration Capability -- 9.7 Manufacturing Format and Scalability -- 9.8 Package Performance -- 9.8.1 Electrical Performance -- 9.8.2 Thermal Performance -- 9.9 Robustness and Reliability Data -- 9.9.1 Automotive Reliability Certification Pass -- 9.9.2 Board Level Reliability Verification Pass -- 9.10 Electrical Test Considerations -- 9.11 Summary -- References -- Chapter 10 Flexible Hybrid Electronics Using Fan-Out Wafer-Level Packaging -- 10.1 Introduction -- 10.2 Recent Trends in Packaging -- 10.3 FHE Using FO-WLP - FlexTrate -- 10.4 Applications on FlexTrate -- Acknowledgments -- References -- Chapter 11 Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations -- 11.1 Introduction -- 11.2 Heterogeneous Interconnect Stitching Technology (HIST) -- 11.3 Thermal Evaluation of 2.5D Integration Using Bridge-Chip Technology -- 11.3.1 2.5D and 3D Benchmark Architectures -- 11.3.1.1 2.5D Integration -- 11.3.1.2 3D Integration -- 11.3.2 Thermal Modeling and Specifications -- 11.3.3 Comparison of Different 2.5D Integration Schemes -- 11.3.4 Thermal Comparison between 2.5D and 3D Integration -- 11.3.5 Thermal Study of Bridge-Chip 2.5D Integration -- 11.3.5.1 Impact of TIM conductivity -- 11.3.5.2 Die Thickness -- 11.3.5.3 Die Spacing -- 11.3.6 Polylithic 3D Integration</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">11.4 Monolithic Microfluidic Cooling of High-Power Electronics -- 11.4.1 Experimental Demonstration and Characterization on Single Die Systems -- 11.4.2 Microfluidic Cooling of 2.5D Devices: Experimental Demonstration -- 11.4.3 Monolithic Microfluidic Cooling of 3D Integration: Modelling Electrical Implications for I/Os -- 11.5 Conclusion -- Acknowledgments -- References -- Index -- EULA.</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Wafer level packaging</subfield><subfield code="0">(DE-588)1058582143</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Wafer level packaging</subfield><subfield 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| id | DE-604.BV048221391 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T19:50:32Z |
| indexdate | 2024-07-10T09:32:24Z |
| institution | BVB |
| isbn | 9781119793847 9781119793892 9781119793908 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-033602128 |
| oclc_num | 1288211078 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-573 |
| owner_facet | DE-91 DE-BY-TUM DE-573 |
| physical | 1 Online-Ressource (xv, 296 Seiten) Illustrationen, Diagramme |
| psigel | ZDB-30-PQE ZDB-35-WEL ZDB-30-PQE TUM_PDA_PQE_Kauf |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | Wiley |
| record_format | marc |
| spelling | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package edited by Beth Keser, Steffen Kröhnert Hoboken, New Jersey Wiley [2022] © 2022 1 Online-Ressource (xv, 296 Seiten) Illustrationen, Diagramme txt rdacontent c rdamedia cr rdacarrier Description based on publisher supplied metadata and other sources Cover -- Title Page -- Copyright -- Contents -- Preface -- Chapter 1 Fan-Out Wafer and Panel Level Packaging Market and Technology Trends -- 1.1 Introduction to Fan-Out Packaging -- 1.1.1 Historical Perspective -- 1.1.2 Key Drivers: Why Fan-Out Packaging? -- 1.1.3 FO-WLP vs. FO-PLP -- 1.1.4 Future of Fan-Out Packaging for Heterogeneous Integration -- 1.2 Market Overview and Applications -- 1.2.1 Fan-Out Packaging Definition -- 1.2.2 Market Segmentation: Core FO vs. HD FO vs. UHD FO -- 1.2.3 Market Valuation: Forecast of Revenue and Volume -- 1.2.4 Current and Future Target Markets -- 1.2.5 Applications of Fan-Out Packaging -- 1.3 Technology Trends and Supply Chain -- 1.3.1 Fan-Out Packaging Technology Roadmaps -- 1.3.2 Fan-Out Packaging Technology by Manufacturer -- 1.3.2.1 Amkor -- 1.3.2.2 JCET -- 1.3.2.3 NXP -- 1.3.2.4 DECA Technologies -- 1.3.2.5 ASE -- 1.3.2.6 TSMC -- 1.3.2.7 PTI -- 1.3.2.8 Samsung Electronics -- 1.3.2.9 Huatian -- 1.3.3 Supply Chain Overview -- 1.3.4 Analysis of the Latest Developments in the Supply Chain -- 1.4 Fan-Out Panel-Level Packaging (FO-PLP) -- 1.4.1 Motivation and Challenges for FO-PLP -- 1.4.2 FO-PLP Market and Applications -- 1.4.3 FO-PLP Supplier Overview -- 1.5 System Device Teardowns -- 1.5.1 Teardown of End-Systems with Fan-Out Packaging -- 1.5.2 Technology Comparison -- 1.5.2.1 Radar IC: eWLB vs. RCP -- 1.5.2.2 MCM/SiP: RCP-SiP vs. eWLB -- 1.5.2.3 PMIC: eWLB vs. M-Series -- 1.5.3 Cost Comparison -- 1.6 Conclusion -- References -- Chapter 2 Cost Comparison of FO-WLP with Other Technologies -- 2.1 Introduction -- 2.2 Activity-Based Cost Modeling -- 2.3 Cost Analysis of FO-WLP Variations -- 2.3.1 Process Segment Costs -- 2.3.1.1 Die Preparation -- 2.3.1.2 Carrier -- 2.3.1.3 Die Bond -- 2.3.1.4 Mold -- 2.3.1.5 Backgrinding -- 2.3.1.6 RDL -- 2.3.1.7 UBM -- 2.3.1.8 Flux and Ball Attach -- 2.3.1.9 Singulation 2.3.2 FO-WLP Variations -- 2.3.2.1 Carrier -- 2.3.2.2 Die Cost and Preparation -- 2.3.2.3 Die Bond -- 2.3.2.4 Mold/Mold + CUF -- 2.3.2.5 Backgrind/Post-mold Grind -- 2.3.2.6 Scrap -- 2.4 Cost of FO-WLP versus Wire Bond and Flip Chip -- 2.5 Package-on-Package Cost Analysis -- 2.6 Conclusions -- References -- Chapter 3 Integrated Fan-Out (InFO) for Mobile Computing -- 3.1 Introduction -- 3.2 Fan-In Wafer-Level Packaging -- 3.2.1 Dielectric and Redistribution Layers (RDL) -- 3.2.2 Under Bump Metallization (UBM) -- 3.2.3 Reliability and Challenges -- 3.2.4 Large Die WLP -- 3.3 Fan-Out Wafer-Level System Integration -- 3.3.1 Chip-First vs. Chip-Last -- 3.3.2 Molding and Planarization -- 3.3.3 Redistribution Layer (RDL) -- 3.3.4 Through Via and Vertical Interconnection -- 3.4 Integrated Passive Devices (IPDs) -- 3.4.1 High Q-Factor 3D Solenoid Inductor -- 3.4.2 Antenna in Package (AiP) and 5G Communication -- 3.4.3 Passive Devices for Millimeter Wave System Integration -- 3.5 Power, Performance, Form Factor, and Cost -- 3.5.1 Signal and Power Integrity -- 3.5.2 Heat Dissipation and Thermal Performance -- 3.5.3 Form Factor and Thickness -- 3.5.4 Cycle Time to Market and Cost -- 3.6 Summary -- References -- Chapter 4 Integrated Fan-Out (InFO) for High Performance Computing -- 4.1 Introduction -- 4.2 3DFabric and System-on-Integrated-Chip (SoIC) -- 4.3 CoWoS-R, CoWoS-S, and CoWoS-L -- 4.4 InFO-L and InFO-R -- 4.5 Info Ultra-High-Density Interconnect (InFO-UHD) -- 4.6 Multi-Stack System Integration (MUST) and Must-in-Must (MiM) -- 4.7 InFO on Substate (InFO-oS) and InFO Local Silicon Interconnect (InFO-L) -- 4.8 InFO with Memory on Substrate (InFO-MS) -- 4.9 InFO 3D Multi-Silicon (InFO-3DMS) and CoWoS-L -- 4.10 InFO System on Wafer (InFO& -- uscore -- SoW) -- 4.11 System on Integrated Substrate (SoIS) -- 4.12 Immersion Memory Compute (ImMC) -- 4.13 Summary References -- Chapter 5 Adaptive Patterning and M-Series for High Density Integration -- 5.1 Technology Description -- 5.2 Applications and Markets -- 5.3 Basic Package Construction -- 5.4 Manufacturing Process Flow and BOM -- 5.5 Design Features and System Integration Capability -- 5.6 Adaptive Patterning -- 5.7 Manufacturing Format and Scalability -- 5.8 Package Performance -- 5.9 Robustness and Reliability Data -- 5.10 Electrical Test Considerations -- 5.11 Summary -- References -- Chapter 6 Panel-Level Packaging for Heterogenous Integration -- 6.1 Introduction -- 6.2 Fan-Out Panel-Level Packaging -- 6.3 Economic Efficiency Analysis of PLP -- 6.4 Summary -- References -- Chapter 7 Next Generation Chip Embedding Technology for High Efficiency Power Modules and Power SiPs -- 7.1 Technology Description -- 7.2 Basic Package Construction -- 7.3 Applications and Markets (HPC, SiP) -- 7.4 Manufacturing Process Flow and BOM -- 7.5 Design Features -- 7.6 System Integration Capability -- 7.7 Package Performance -- 7.8 Robustness and Reliability Data -- 7.9 Electrical Test Considerations -- 7.10 Summary -- References -- Chapter 8 Die Integration Technologies on Advanced Substrates Including Embedding and Cavities -- 8.1 Introduction -- 8.2 Heterogeneous Integration by Use of Embedded Chip Packaging (ECP) -- 8.3 Embedding Process -- 8.4 Component Selection -- 8.5 Design Technology -- 8.6 Testing -- 8.7 Applications for ECP Technology -- 8.8 Heterogeneous Integration Using Cavities in PCB -- 8.9 Package Performance, Robustness, and Reliability -- 8.10 Conclusion -- References -- Chapter 9 Advanced Embedded Trace Substrate - A Flexible Alternative to Fan-Out Wafer Level Packaging -- 9.1 Technology Description -- 9.1.1 C2iM Technology -- 9.1.2 C2iM-PLP Technology -- 9.2 Applications and Markets -- 9.3 Basic Package Construction -- 9.3.1 C2iM-PLP Experience 9.3.2 C2iM-PLP Advantages and Disadvantages Compared to Wirebond Quad Flat No Lead (WB-QFN) and Flip-Chip QFN (FC-QFN) Packages -- 9.3.3 C2iM-PLP Advantages and Disadvantages Compared to WLP and FO-WLP -- 9.3.4 Future Applications -- 9.3.5 Limitations of C2iM-PLP -- 9.4 Manufacturing Process Flow and BOM -- 9.5 Design Features -- 9.5.1 Package Design Rules -- 9.5.2 Design Rules for Die UBM -- 9.5.3 Design Rules for Die Side by Side -- 9.5.4 Design Rules for Cu Pillar -- 9.6 System Integration Capability -- 9.7 Manufacturing Format and Scalability -- 9.8 Package Performance -- 9.8.1 Electrical Performance -- 9.8.2 Thermal Performance -- 9.9 Robustness and Reliability Data -- 9.9.1 Automotive Reliability Certification Pass -- 9.9.2 Board Level Reliability Verification Pass -- 9.10 Electrical Test Considerations -- 9.11 Summary -- References -- Chapter 10 Flexible Hybrid Electronics Using Fan-Out Wafer-Level Packaging -- 10.1 Introduction -- 10.2 Recent Trends in Packaging -- 10.3 FHE Using FO-WLP - FlexTrate -- 10.4 Applications on FlexTrate -- Acknowledgments -- References -- Chapter 11 Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations -- 11.1 Introduction -- 11.2 Heterogeneous Interconnect Stitching Technology (HIST) -- 11.3 Thermal Evaluation of 2.5D Integration Using Bridge-Chip Technology -- 11.3.1 2.5D and 3D Benchmark Architectures -- 11.3.1.1 2.5D Integration -- 11.3.1.2 3D Integration -- 11.3.2 Thermal Modeling and Specifications -- 11.3.3 Comparison of Different 2.5D Integration Schemes -- 11.3.4 Thermal Comparison between 2.5D and 3D Integration -- 11.3.5 Thermal Study of Bridge-Chip 2.5D Integration -- 11.3.5.1 Impact of TIM conductivity -- 11.3.5.2 Die Thickness -- 11.3.5.3 Die Spacing -- 11.3.6 Polylithic 3D Integration 11.4 Monolithic Microfluidic Cooling of High-Power Electronics -- 11.4.1 Experimental Demonstration and Characterization on Single Die Systems -- 11.4.2 Microfluidic Cooling of 2.5D Devices: Experimental Demonstration -- 11.4.3 Monolithic Microfluidic Cooling of 3D Integration: Modelling Electrical Implications for I/Os -- 11.5 Conclusion -- Acknowledgments -- References -- Index -- EULA. Wafer level packaging (DE-588)1058582143 gnd rswk-swf Wafer level packaging (DE-588)1058582143 s DE-604 Keser, Beth edt Kröhnert, Steffen edt Erscheint auch als Kröhnert, Steffen Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces Newark : John Wiley & Sons, Incorporated,c2021 Druck-Ausgabe 978-1-119-79377-9 |
| spellingShingle | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package Cover -- Title Page -- Copyright -- Contents -- Preface -- Chapter 1 Fan-Out Wafer and Panel Level Packaging Market and Technology Trends -- 1.1 Introduction to Fan-Out Packaging -- 1.1.1 Historical Perspective -- 1.1.2 Key Drivers: Why Fan-Out Packaging? -- 1.1.3 FO-WLP vs. FO-PLP -- 1.1.4 Future of Fan-Out Packaging for Heterogeneous Integration -- 1.2 Market Overview and Applications -- 1.2.1 Fan-Out Packaging Definition -- 1.2.2 Market Segmentation: Core FO vs. HD FO vs. UHD FO -- 1.2.3 Market Valuation: Forecast of Revenue and Volume -- 1.2.4 Current and Future Target Markets -- 1.2.5 Applications of Fan-Out Packaging -- 1.3 Technology Trends and Supply Chain -- 1.3.1 Fan-Out Packaging Technology Roadmaps -- 1.3.2 Fan-Out Packaging Technology by Manufacturer -- 1.3.2.1 Amkor -- 1.3.2.2 JCET -- 1.3.2.3 NXP -- 1.3.2.4 DECA Technologies -- 1.3.2.5 ASE -- 1.3.2.6 TSMC -- 1.3.2.7 PTI -- 1.3.2.8 Samsung Electronics -- 1.3.2.9 Huatian -- 1.3.3 Supply Chain Overview -- 1.3.4 Analysis of the Latest Developments in the Supply Chain -- 1.4 Fan-Out Panel-Level Packaging (FO-PLP) -- 1.4.1 Motivation and Challenges for FO-PLP -- 1.4.2 FO-PLP Market and Applications -- 1.4.3 FO-PLP Supplier Overview -- 1.5 System Device Teardowns -- 1.5.1 Teardown of End-Systems with Fan-Out Packaging -- 1.5.2 Technology Comparison -- 1.5.2.1 Radar IC: eWLB vs. RCP -- 1.5.2.2 MCM/SiP: RCP-SiP vs. eWLB -- 1.5.2.3 PMIC: eWLB vs. M-Series -- 1.5.3 Cost Comparison -- 1.6 Conclusion -- References -- Chapter 2 Cost Comparison of FO-WLP with Other Technologies -- 2.1 Introduction -- 2.2 Activity-Based Cost Modeling -- 2.3 Cost Analysis of FO-WLP Variations -- 2.3.1 Process Segment Costs -- 2.3.1.1 Die Preparation -- 2.3.1.2 Carrier -- 2.3.1.3 Die Bond -- 2.3.1.4 Mold -- 2.3.1.5 Backgrinding -- 2.3.1.6 RDL -- 2.3.1.7 UBM -- 2.3.1.8 Flux and Ball Attach -- 2.3.1.9 Singulation 2.3.2 FO-WLP Variations -- 2.3.2.1 Carrier -- 2.3.2.2 Die Cost and Preparation -- 2.3.2.3 Die Bond -- 2.3.2.4 Mold/Mold + CUF -- 2.3.2.5 Backgrind/Post-mold Grind -- 2.3.2.6 Scrap -- 2.4 Cost of FO-WLP versus Wire Bond and Flip Chip -- 2.5 Package-on-Package Cost Analysis -- 2.6 Conclusions -- References -- Chapter 3 Integrated Fan-Out (InFO) for Mobile Computing -- 3.1 Introduction -- 3.2 Fan-In Wafer-Level Packaging -- 3.2.1 Dielectric and Redistribution Layers (RDL) -- 3.2.2 Under Bump Metallization (UBM) -- 3.2.3 Reliability and Challenges -- 3.2.4 Large Die WLP -- 3.3 Fan-Out Wafer-Level System Integration -- 3.3.1 Chip-First vs. Chip-Last -- 3.3.2 Molding and Planarization -- 3.3.3 Redistribution Layer (RDL) -- 3.3.4 Through Via and Vertical Interconnection -- 3.4 Integrated Passive Devices (IPDs) -- 3.4.1 High Q-Factor 3D Solenoid Inductor -- 3.4.2 Antenna in Package (AiP) and 5G Communication -- 3.4.3 Passive Devices for Millimeter Wave System Integration -- 3.5 Power, Performance, Form Factor, and Cost -- 3.5.1 Signal and Power Integrity -- 3.5.2 Heat Dissipation and Thermal Performance -- 3.5.3 Form Factor and Thickness -- 3.5.4 Cycle Time to Market and Cost -- 3.6 Summary -- References -- Chapter 4 Integrated Fan-Out (InFO) for High Performance Computing -- 4.1 Introduction -- 4.2 3DFabric and System-on-Integrated-Chip (SoIC) -- 4.3 CoWoS-R, CoWoS-S, and CoWoS-L -- 4.4 InFO-L and InFO-R -- 4.5 Info Ultra-High-Density Interconnect (InFO-UHD) -- 4.6 Multi-Stack System Integration (MUST) and Must-in-Must (MiM) -- 4.7 InFO on Substate (InFO-oS) and InFO Local Silicon Interconnect (InFO-L) -- 4.8 InFO with Memory on Substrate (InFO-MS) -- 4.9 InFO 3D Multi-Silicon (InFO-3DMS) and CoWoS-L -- 4.10 InFO System on Wafer (InFO& -- uscore -- SoW) -- 4.11 System on Integrated Substrate (SoIS) -- 4.12 Immersion Memory Compute (ImMC) -- 4.13 Summary References -- Chapter 5 Adaptive Patterning and M-Series for High Density Integration -- 5.1 Technology Description -- 5.2 Applications and Markets -- 5.3 Basic Package Construction -- 5.4 Manufacturing Process Flow and BOM -- 5.5 Design Features and System Integration Capability -- 5.6 Adaptive Patterning -- 5.7 Manufacturing Format and Scalability -- 5.8 Package Performance -- 5.9 Robustness and Reliability Data -- 5.10 Electrical Test Considerations -- 5.11 Summary -- References -- Chapter 6 Panel-Level Packaging for Heterogenous Integration -- 6.1 Introduction -- 6.2 Fan-Out Panel-Level Packaging -- 6.3 Economic Efficiency Analysis of PLP -- 6.4 Summary -- References -- Chapter 7 Next Generation Chip Embedding Technology for High Efficiency Power Modules and Power SiPs -- 7.1 Technology Description -- 7.2 Basic Package Construction -- 7.3 Applications and Markets (HPC, SiP) -- 7.4 Manufacturing Process Flow and BOM -- 7.5 Design Features -- 7.6 System Integration Capability -- 7.7 Package Performance -- 7.8 Robustness and Reliability Data -- 7.9 Electrical Test Considerations -- 7.10 Summary -- References -- Chapter 8 Die Integration Technologies on Advanced Substrates Including Embedding and Cavities -- 8.1 Introduction -- 8.2 Heterogeneous Integration by Use of Embedded Chip Packaging (ECP) -- 8.3 Embedding Process -- 8.4 Component Selection -- 8.5 Design Technology -- 8.6 Testing -- 8.7 Applications for ECP Technology -- 8.8 Heterogeneous Integration Using Cavities in PCB -- 8.9 Package Performance, Robustness, and Reliability -- 8.10 Conclusion -- References -- Chapter 9 Advanced Embedded Trace Substrate - A Flexible Alternative to Fan-Out Wafer Level Packaging -- 9.1 Technology Description -- 9.1.1 C2iM Technology -- 9.1.2 C2iM-PLP Technology -- 9.2 Applications and Markets -- 9.3 Basic Package Construction -- 9.3.1 C2iM-PLP Experience 9.3.2 C2iM-PLP Advantages and Disadvantages Compared to Wirebond Quad Flat No Lead (WB-QFN) and Flip-Chip QFN (FC-QFN) Packages -- 9.3.3 C2iM-PLP Advantages and Disadvantages Compared to WLP and FO-WLP -- 9.3.4 Future Applications -- 9.3.5 Limitations of C2iM-PLP -- 9.4 Manufacturing Process Flow and BOM -- 9.5 Design Features -- 9.5.1 Package Design Rules -- 9.5.2 Design Rules for Die UBM -- 9.5.3 Design Rules for Die Side by Side -- 9.5.4 Design Rules for Cu Pillar -- 9.6 System Integration Capability -- 9.7 Manufacturing Format and Scalability -- 9.8 Package Performance -- 9.8.1 Electrical Performance -- 9.8.2 Thermal Performance -- 9.9 Robustness and Reliability Data -- 9.9.1 Automotive Reliability Certification Pass -- 9.9.2 Board Level Reliability Verification Pass -- 9.10 Electrical Test Considerations -- 9.11 Summary -- References -- Chapter 10 Flexible Hybrid Electronics Using Fan-Out Wafer-Level Packaging -- 10.1 Introduction -- 10.2 Recent Trends in Packaging -- 10.3 FHE Using FO-WLP - FlexTrate -- 10.4 Applications on FlexTrate -- Acknowledgments -- References -- Chapter 11 Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations -- 11.1 Introduction -- 11.2 Heterogeneous Interconnect Stitching Technology (HIST) -- 11.3 Thermal Evaluation of 2.5D Integration Using Bridge-Chip Technology -- 11.3.1 2.5D and 3D Benchmark Architectures -- 11.3.1.1 2.5D Integration -- 11.3.1.2 3D Integration -- 11.3.2 Thermal Modeling and Specifications -- 11.3.3 Comparison of Different 2.5D Integration Schemes -- 11.3.4 Thermal Comparison between 2.5D and 3D Integration -- 11.3.5 Thermal Study of Bridge-Chip 2.5D Integration -- 11.3.5.1 Impact of TIM conductivity -- 11.3.5.2 Die Thickness -- 11.3.5.3 Die Spacing -- 11.3.6 Polylithic 3D Integration 11.4 Monolithic Microfluidic Cooling of High-Power Electronics -- 11.4.1 Experimental Demonstration and Characterization on Single Die Systems -- 11.4.2 Microfluidic Cooling of 2.5D Devices: Experimental Demonstration -- 11.4.3 Monolithic Microfluidic Cooling of 3D Integration: Modelling Electrical Implications for I/Os -- 11.5 Conclusion -- Acknowledgments -- References -- Index -- EULA. Wafer level packaging (DE-588)1058582143 gnd |
| subject_GND | (DE-588)1058582143 |
| title | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package |
| title_auth | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package |
| title_exact_search | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package |
| title_exact_search_txtP | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package |
| title_full | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package edited by Beth Keser, Steffen Kröhnert |
| title_fullStr | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package edited by Beth Keser, Steffen Kröhnert |
| title_full_unstemmed | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces high performance compute and system-in-package edited by Beth Keser, Steffen Kröhnert |
| title_short | Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces |
| title_sort | embedded and fan out wafer and panel level packaging technologies for advanced application spaces high performance compute and system in package |
| title_sub | high performance compute and system-in-package |
| topic | Wafer level packaging (DE-588)1058582143 gnd |
| topic_facet | Wafer level packaging |
| work_keys_str_mv | AT keserbeth embeddedandfanoutwaferandpanellevelpackagingtechnologiesforadvancedapplicationspaceshighperformancecomputeandsysteminpackage AT krohnertsteffen embeddedandfanoutwaferandpanellevelpackagingtechnologiesforadvancedapplicationspaceshighperformancecomputeandsysteminpackage |