Digital Logic Design Using Verilog: Coding and RTL Synthesis
Gespeichert in:
1. Verfasser: | |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Singapore
Springer Singapore
2022
Singapore Springer |
Ausgabe: | Second Edition |
Schlagworte: | |
Online-Zugang: | BTU01 FAB01 FAW01 FHA01 FHD01 FHI01 FHM01 FHN01 FHR01 FKE01 FLA01 FRO01 FWS01 FWS02 HTW01 TUM01 UBY01 UER01 Volltext |
Beschreibung: | 1 Online-Ressource (XXV, 604 Seiten) |
ISBN: | 9789811631993 |
DOI: | 10.1007/978-981-16-3199-3 |
Internformat
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Datensatz im Suchindex
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discipline_str_mv | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik Maschinenbau |
doi_str_mv | 10.1007/978-981-16-3199-3 |
edition | Second Edition |
format | Electronic eBook |
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id | DE-604.BV047832894 |
illustrated | Not Illustrated |
index_date | 2024-07-03T19:09:30Z |
indexdate | 2024-08-01T16:15:38Z |
institution | BVB |
isbn | 9789811631993 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-033216128 |
oclc_num | 1298745525 |
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owner | DE-860 DE-91 DE-BY-TUM DE-1046 DE-1043 DE-Aug4 DE-898 DE-BY-UBR DE-861 DE-523 DE-859 DE-29 DE-863 DE-BY-FWS DE-1050 DE-862 DE-BY-FWS DE-92 DE-573 DE-M347 DE-706 DE-634 DE-83 |
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physical | 1 Online-Ressource (XXV, 604 Seiten) |
psigel | ZDB-2-ENG ZDB-2-ENG_2022 |
publishDate | 2022 |
publishDateSearch | 2022 |
publishDateSort | 2022 |
publisher | Springer Singapore Springer |
record_format | marc |
spellingShingle | Taraate, Vaibbhav Digital Logic Design Using Verilog Coding and RTL Synthesis Electronic Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Electronic circuits Electronics Logic design |
title | Digital Logic Design Using Verilog Coding and RTL Synthesis |
title_auth | Digital Logic Design Using Verilog Coding and RTL Synthesis |
title_exact_search | Digital Logic Design Using Verilog Coding and RTL Synthesis |
title_exact_search_txtP | Digital Logic Design Using Verilog Coding and RTL Synthesis |
title_full | Digital Logic Design Using Verilog Coding and RTL Synthesis Vaibbhav Taraate |
title_fullStr | Digital Logic Design Using Verilog Coding and RTL Synthesis Vaibbhav Taraate |
title_full_unstemmed | Digital Logic Design Using Verilog Coding and RTL Synthesis Vaibbhav Taraate |
title_short | Digital Logic Design Using Verilog |
title_sort | digital logic design using verilog coding and rtl synthesis |
title_sub | Coding and RTL Synthesis |
topic | Electronic Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Electronic circuits Electronics Logic design |
topic_facet | Electronic Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Electronic circuits Electronics Logic design |
url | https://doi.org/10.1007/978-981-16-3199-3 |
work_keys_str_mv | AT taraatevaibbhav digitallogicdesignusingverilogcodingandrtlsynthesis |