APA-Zitierstil (7. Ausg.)

Taraate, V. (2022). Digital Logic Design Using Verilog: Coding and RTL Synthesis (Second Edition.). Springer Singapore. https://doi.org/10.1007/978-981-16-3199-3

Chicago-Zitierstil (17. Ausg.)

Taraate, Vaibbhav. Digital Logic Design Using Verilog: Coding and RTL Synthesis. Second Edition. Singapore: Springer Singapore, 2022. https://doi.org/10.1007/978-981-16-3199-3.

MLA-Zitierstil (9. Ausg.)

Taraate, Vaibbhav. Digital Logic Design Using Verilog: Coding and RTL Synthesis. Second Edition. Springer Singapore, 2022. https://doi.org/10.1007/978-981-16-3199-3.