Dual port SRAM - clock cycle and precharge:
Course content reaffirmed: 06/2015--A synchronous RAM is activated on the rising edge of clock and basically has 2 main internal cycles: the active cycle when the read or write is occurring and the pre-charge cycle that sets up the initial conditions for the next new clock cycle. The timing requirem...
Saved in:
| Main Author: | |
|---|---|
| Format: | Electronic Video |
| Language: | English |
| Published: |
United States
IEEE
2011
|
| Subjects: | |
| Online Access: | FHN01 TUM01 |
| Summary: | Course content reaffirmed: 06/2015--A synchronous RAM is activated on the rising edge of clock and basically has 2 main internal cycles: the active cycle when the read or write is occurring and the pre-charge cycle that sets up the initial conditions for the next new clock cycle. The timing requirements and relationships that the customer must meet will first be reviewed with a specific focus on the clock cycle. The key internal signals of the word line and the pre-charging of the bit lines and their relationship will be discussed along with the pre-charge circuitry. The timing interaction and relationships between the 2 ports must be kept in mind |
| Item Description: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) |
| Physical Description: | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
| ISBN: | 9781612845166 |
Staff View
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| indexdate | 2024-07-10T09:13:11Z |
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| isbn | 9781612845166 |
| language | English |
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| spelling | Sheppard, Doug Verfasser aut Dual port SRAM - clock cycle and precharge Doug Sheppard Dual port static random-access memory - clock cycle and precharge United States IEEE 2011 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) Course content reaffirmed: 06/2015--A synchronous RAM is activated on the rising edge of clock and basically has 2 main internal cycles: the active cycle when the read or write is occurring and the pre-charge cycle that sets up the initial conditions for the next new clock cycle. The timing requirements and relationships that the customer must meet will first be reviewed with a specific focus on the clock cycle. The key internal signals of the word line and the pre-charging of the bit lines and their relationship will be discussed along with the pre-charge circuitry. The timing interaction and relationships between the 2 ports must be kept in mind Data processing Random access memory Synchronization Simulation (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug Dual port SRAM - clock cycle and precharge Data processing Random access memory Synchronization Simulation |
| subject_GND | (DE-588)4017102-4 |
| title | Dual port SRAM - clock cycle and precharge |
| title_alt | Dual port static random-access memory - clock cycle and precharge |
| title_auth | Dual port SRAM - clock cycle and precharge |
| title_exact_search | Dual port SRAM - clock cycle and precharge |
| title_exact_search_txtP | Dual port SRAM - clock cycle and precharge |
| title_full | Dual port SRAM - clock cycle and precharge Doug Sheppard |
| title_fullStr | Dual port SRAM - clock cycle and precharge Doug Sheppard |
| title_full_unstemmed | Dual port SRAM - clock cycle and precharge Doug Sheppard |
| title_short | Dual port SRAM - clock cycle and precharge |
| title_sort | dual port sram clock cycle and precharge |
| topic | Data processing Random access memory Synchronization Simulation |
| topic_facet | Data processing Random access memory Synchronization Simulation Film |
| work_keys_str_mv | AT shepparddoug dualportsramclockcycleandprecharge AT shepparddoug dualportstaticrandomaccessmemoryclockcycleandprecharge |