Dual port SRAM - memory architecture:
Course content reaffirmed: 06/2015--The sub-blocks of the dual port memory architecture is presented in the tutorial with a key focus on the path from the array bit lines to the data pins for both the read and write. A memory can have many possibilities of how the bits and bits per word is configure...
Saved in:
| Main Author: | |
|---|---|
| Format: | Electronic Video |
| Language: | English |
| Published: |
United States
IEEE
2011
|
| Subjects: | |
| Online Access: | FHN01 TUM01 |
| Summary: | Course content reaffirmed: 06/2015--The sub-blocks of the dual port memory architecture is presented in the tutorial with a key focus on the path from the array bit lines to the data pins for both the read and write. A memory can have many possibilities of how the bits and bits per word is configured which is based on the number of rows and columns in the array. All of the key blocks required to decode the columns, sense the data, select and decode the sense amp and drive the Data Out pin for a read from the bit lines are discussed. The write path from the Data In pin up through the column decode and write select circuitry is also presented |
| Item Description: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) |
| Physical Description: | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
| ISBN: | 9781612845159 |
Staff View
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| spelling | Sheppard, Doug Verfasser aut Dual port SRAM - memory architecture Doug Sheppard Dual port static random-access memory - memory architecture United States IEEE 2011 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) Course content reaffirmed: 06/2015--The sub-blocks of the dual port memory architecture is presented in the tutorial with a key focus on the path from the array bit lines to the data pins for both the read and write. A memory can have many possibilities of how the bits and bits per word is configured which is based on the number of rows and columns in the array. All of the key blocks required to decode the columns, sense the data, select and decode the sense amp and drive the Data Out pin for a read from the bit lines are discussed. The write path from the Data In pin up through the column decode and write select circuitry is also presented Random access memory Logic design Configuration management Computer architecture (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug Dual port SRAM - memory architecture Random access memory Logic design Configuration management Computer architecture |
| subject_GND | (DE-588)4017102-4 |
| title | Dual port SRAM - memory architecture |
| title_alt | Dual port static random-access memory - memory architecture |
| title_auth | Dual port SRAM - memory architecture |
| title_exact_search | Dual port SRAM - memory architecture |
| title_exact_search_txtP | Dual port SRAM - memory architecture |
| title_full | Dual port SRAM - memory architecture Doug Sheppard |
| title_fullStr | Dual port SRAM - memory architecture Doug Sheppard |
| title_full_unstemmed | Dual port SRAM - memory architecture Doug Sheppard |
| title_short | Dual port SRAM - memory architecture |
| title_sort | dual port sram memory architecture |
| topic | Random access memory Logic design Configuration management Computer architecture |
| topic_facet | Random access memory Logic design Configuration management Computer architecture Film |
| work_keys_str_mv | AT shepparddoug dualportsrammemoryarchitecture AT shepparddoug dualportstaticrandomaccessmemorymemoryarchitecture |