Course content reaffirmed: 06/2015--This is the final tutorial in the series of tutorials on the Single Port SRAM design, and is the final step in the full circuit analysis that was done by a design engineer before the design was built in the fab. There are many subtleties to be considered when runn...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Sheppard, Doug (VerfasserIn)
Format:	Elektronisch Video
Sprache:	English
Veröffentlicht:	United States IEEE 2010
Schlagworte:	Integrated circuits Random access memory Film
Online-Zugang:	FHN01 TUM01
Zusammenfassung:	Course content reaffirmed: 06/2015--This is the final tutorial in the series of tutorials on the Single Port SRAM design, and is the final step in the full circuit analysis that was done by a design engineer before the design was built in the fab. There are many subtleties to be considered when running full circuit simulations on memories with the main goal of analyzing the weakest portions of the design and evaluating how much margin there is under worst case situations. Combinations of cycles must be considered to determine how a previous cycle can affect the quality of the next cycle. Location of the memory cell accessed in the old and new cycle, old data vs. new data, write cycle effects on the next read cycle are all evaluated in this tutorial. Results of SPICE simulations and waveforms will be presented along with discussion of the top level simulation schematic that must accurately model the loading by all cells on signal nodes in the layout
Beschreibung:	Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020)
Beschreibung:	1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations
ISBN:	9781424462063