SRAM design - control circuitry:
Course content reaffirmed: 06/2015--The previous tutorials in this series focused on the design of individual circuits. Now we begin putting it all together. This tutorial will focus on the interaction between the circuits and their key timing relationships by comparing the individual timing paths....
Saved in:
| Main Author: | |
|---|---|
| Format: | Electronic Video |
| Language: | English |
| Published: |
United States
IEEE
2010
|
| Subjects: | |
| Online Access: | FHN01 TUM01 |
| Summary: | Course content reaffirmed: 06/2015--The previous tutorials in this series focused on the design of individual circuits. Now we begin putting it all together. This tutorial will focus on the interaction between the circuits and their key timing relationships by comparing the individual timing paths. The control circuit will be designed to create: global signals for activating the word lines, passing and latching the address, set-up time, hold time, enabling and disabling pre-charge, read select timing and write select timing. Adhering to a fanout of 4 will greatly aid in quickly evaluating each timing path without initially needing to run SPICE simulations |
| Item Description: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020) |
| Physical Description: | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
| ISBN: | 9781424461776 |
Staff View
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| spelling | Sheppard, Doug Verfasser aut SRAM design - control circuitry Doug Sheppard Static random-access memory design - control circuitry United States IEEE 2010 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020) Course content reaffirmed: 06/2015--The previous tutorials in this series focused on the design of individual circuits. Now we begin putting it all together. This tutorial will focus on the interaction between the circuits and their key timing relationships by comparing the individual timing paths. The control circuit will be designed to create: global signals for activating the word lines, passing and latching the address, set-up time, hold time, enabling and disabling pre-charge, read select timing and write select timing. Adhering to a fanout of 4 will greatly aid in quickly evaluating each timing path without initially needing to run SPICE simulations Integrated circuits Signal processing Data processing Random access memory (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug SRAM design - control circuitry Integrated circuits Signal processing Data processing Random access memory |
| subject_GND | (DE-588)4017102-4 |
| title | SRAM design - control circuitry |
| title_alt | Static random-access memory design - control circuitry |
| title_auth | SRAM design - control circuitry |
| title_exact_search | SRAM design - control circuitry |
| title_exact_search_txtP | SRAM design - control circuitry |
| title_full | SRAM design - control circuitry Doug Sheppard |
| title_fullStr | SRAM design - control circuitry Doug Sheppard |
| title_full_unstemmed | SRAM design - control circuitry Doug Sheppard |
| title_short | SRAM design - control circuitry |
| title_sort | sram design control circuitry |
| topic | Integrated circuits Signal processing Data processing Random access memory |
| topic_facet | Integrated circuits Signal processing Data processing Random access memory Film |
| work_keys_str_mv | AT shepparddoug sramdesigncontrolcircuitry AT shepparddoug staticrandomaccessmemorydesigncontrolcircuitry |