SRAM design - row decoder:
Course content reaffirmed: 06/2015--The access of a memory cell starts when the Word Line is asserted which is controlled by the Word Line Driver and the Row Decoder. This tutorial will focus on the design of the Row Decoder starting with an overview of a basic decoder, and then will describe a grea...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch Video |
| Sprache: | English |
| Veröffentlicht: |
United States
IEEE
2009
|
| Schlagworte: | |
| Online-Zugang: | FHN01 TUM01 |
| Zusammenfassung: | Course content reaffirmed: 06/2015--The access of a memory cell starts when the Word Line is asserted which is controlled by the Word Line Driver and the Row Decoder. This tutorial will focus on the design of the Row Decoder starting with an overview of a basic decoder, and then will describe a greatly improved version that is faster and presents a smaller load to the Address Buffers. The Word Line Driver will be designed such that it is controlled by an internal clock which is critical to the overall timing associated with reading and writing the memory cell. Additional enhancements to the Word Line Driver will be made to reduce the layout area so that it can fit in the small pitch of a memory cell and have increased performance |
| Beschreibung: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020) |
| Beschreibung: | 1 Online-Resource (1 Videodatei, 60 Minuten) |
| ISBN: | 9781424461394 |
Internformat
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Datensatz im Suchindex
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| dewey-raw | 621.38173 |
| dewey-search | 621.38173 |
| dewey-sort | 3621.38173 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| isbn | 9781424461394 |
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| spelling | Sheppard, Doug Verfasser aut SRAM design - row decoder Doug Sheppard Static random-access memory design - row decoder United States IEEE 2009 1 Online-Resource (1 Videodatei, 60 Minuten) tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020) Course content reaffirmed: 06/2015--The access of a memory cell starts when the Word Line is asserted which is controlled by the Word Line Driver and the Row Decoder. This tutorial will focus on the design of the Row Decoder starting with an overview of a basic decoder, and then will describe a greatly improved version that is faster and presents a smaller load to the Address Buffers. The Word Line Driver will be designed such that it is controlled by an internal clock which is critical to the overall timing associated with reading and writing the memory cell. Additional enhancements to the Word Line Driver will be made to reduce the layout area so that it can fit in the small pitch of a memory cell and have increased performance Integrated circuits Random access memory Data processing Signal processing (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug SRAM design - row decoder Integrated circuits Random access memory Data processing Signal processing |
| subject_GND | (DE-588)4017102-4 |
| title | SRAM design - row decoder |
| title_alt | Static random-access memory design - row decoder |
| title_auth | SRAM design - row decoder |
| title_exact_search | SRAM design - row decoder |
| title_exact_search_txtP | SRAM design - row decoder |
| title_full | SRAM design - row decoder Doug Sheppard |
| title_fullStr | SRAM design - row decoder Doug Sheppard |
| title_full_unstemmed | SRAM design - row decoder Doug Sheppard |
| title_short | SRAM design - row decoder |
| title_sort | sram design row decoder |
| topic | Integrated circuits Random access memory Data processing Signal processing |
| topic_facet | Integrated circuits Random access memory Data processing Signal processing Film |
| work_keys_str_mv | AT shepparddoug sramdesignrowdecoder AT shepparddoug staticrandomaccessmemorydesignrowdecoder |