SRAM design - mux factor and data buffer:

Course content reaffirmed: 06/2015--This tutorial continues the design of the read path from the output of the sense amp through the Data Out Buffer into the data out driver and eventually to the pad that the customer connects to. The dual use of the sense amp clock signal is discussed whereby it cr...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Sheppard, Doug (VerfasserIn)
Format: Elektronisch Video
Sprache:English
Veröffentlicht: United States IEEE 2009
Schlagworte:
Online-Zugang:FHN01
TUM01
Zusammenfassung:Course content reaffirmed: 06/2015--This tutorial continues the design of the read path from the output of the sense amp through the Data Out Buffer into the data out driver and eventually to the pad that the customer connects to. The dual use of the sense amp clock signal is discussed whereby it creates an additional 1 of 2 decode that results in a mux factor of four. Other mux factors will be designed to allow for a reconfigurable memory. A new control signal called Output Enable will be discussed and will be designed into the Data Out Buffer for controlling how the SRAM drives the data out pad. As always, plots of the layout and an extracted SPICE netlist from layout will be included
Beschreibung:Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020)
Beschreibung:1 Online-Resource (1 Videodatei, 60 Minuten)
ISBN:9781424461332

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