Course content reaffirmed: 06/2015--A good design approach is to first consider the read cycle by designing the read path from the memory cell all the way out to the Data Out Pad. This tutorial takes the small signal that the memory cell creates and focuses on the Sensing Scheme that is required to...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Sheppard, Doug (VerfasserIn)
Format:	Elektronisch Video
Sprache:	English
Veröffentlicht:	United States IEEE 2009
Schlagworte:	Integrated circuits Random access memory Data processing Signal processing Film
Online-Zugang:	FHN01 TUM01
Zusammenfassung:	Course content reaffirmed: 06/2015--A good design approach is to first consider the read cycle by designing the read path from the memory cell all the way out to the Data Out Pad. This tutorial takes the small signal that the memory cell creates and focuses on the Sensing Scheme that is required to create the gain necessary to create a full CMOS level. The function and design of the Sense Amp will be discussed in detail as well as the key requirements of the various control signals, some of which have dual purposes such as controlling precharge and performing a 1 of 2 decode. There are many subtle things that must be considered and analyzed when designing the Sensing Scheme, not only in the schematics but in the layout as well. As such, portions of the layout will be reviewed along with an approach that eliminates noise that could cause it to fail. Plots of the layout will be provided along with an extracted SPICE netlist. Waveforms from the SPICE simulation will also be reviewed. Suggested order for proceeding through the IEEE eLearning Series on Design of Integrated Circuits tutorials: 1. Integrated Circuit Digital Design Methodology; 2. Integrated Circuit Digital Design Methodology - Advanced Analysis and Simulation; 3. SRAM Design - Overview and Memory Cell Division; 4. SRAM Design - Array Design and Precharge; 5. SRAM Design - Sensing Scheme; 6. SRAM Design - MUX Factor and Data Buffer; 7. SRAM Design - Write Path; 8. SRAM Design - ROW Decoder; 9. SRAM Design - Address Buffer; 10. SRAM Design - Clock Buffer; 11. SRAM Design - Control Circuitry; 12. SRAM Design - Sensing and Write Control
Beschreibung:	Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 10, 2020)
Beschreibung:	1 Online-Resource (1 Videodatei, 60 Minuten)
ISBN:	9781424461301