Computer organization and design: the hardware software interface
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cambridge, MA
Morgan Kaufmann
[2021]
|
| Ausgabe: | RISC-V edition, second edition |
| Schriftenreihe: | [The Morgan Kaufmann series in computer architecture and design]
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | 1 Band (verschiedene Seitenzählungen) Illustrationen |
| ISBN: | 9780128203316 |
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Datensatz im Suchindex
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Contents Preface xi CHAPTERS Computer Abstractions and Technology 2 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 Introduction 3 Seven Great Ideas in Computer Architecture 10 Below Your Program 13 Under the Covers 16 Technologies for Building Processors and Memory 25 Performance 29 The Power Wall 40 The Sea Change: The Switch from Uniprocessors to Multiprocessors Real Stuff: Benchmarking the Intel Core І7 46 Going Faster: Matrix Multiply in Python 49 Fallacies and Pitfalls 50 Concluding Remarks 53 Historical Perspective and Further Reading 55 Self-Study 55 Exercises 59 Instructions: Language of the Computer 66 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Introduction 68 Operations of the Computer Hardware 69 Operands of the Computer Hardware 73 Signed and Unsigned Numbers 80 Representing Instructions in the Computer 87 Logical Operations 95 Instructions for Making Decisions 98 Supporting Procedures in Computer Hardware 104 Communicating with People 114 RISC-V Addressing for Wide Immediates and Addresses Parallelism and Instructions: Synchronization 128 Translating and Starting a Program 131 AC Sort Example to Put it Ah Together 140 120
Contents 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.26 Arrays versus Pointers 148 Advanced Material: Compiling C and Interpreting Java 151 Real Stuff: MIPS Instructions 152 Real Stuff: ARMv7 (32-bit) Instructions 153 Real Stuff ARMv8 (64-bit) Instructions 157 Real Stuff: x86 Instructions 158 Real Stuff: The Rest of the RISC-V Instruction Set 167 Going Faster: Matrix Multiply in C 168 Fallacies and Pitfalls 170 Concluding Remarks 172 Historical Perspective and Further Reading 174 Self-Study 175 Exercises 178 Arithmetic for Computers 188 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 Introduction 190 Addition and Subtraction 190 Multiplication 193 Division 199 Floating Point 208 Parallelism and Computer Arithmetic: Subword Parallelism 233 Real Stuff Streaming SĪMD Extensions and Advanced Vector Extensions in x86 234 Going Faster: Subword Parallelism and Matrix Multiply 236 Fallacies and Pitfalls 238 Concluding Remarks 241 Historical Perspective and Further Reading 242 Self-Study 242 Exercises 246 The Processor 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 252 Introduction 254 Logic Design Conventions 258 Building a Datapath 261 A Simple Implementation Scheme 269 Multicyle Implementation 282 An Overview of Pipelining 283 Pipelined Datapath and Control 296 Data Hazards: Forwarding versus Stalling 313 Control Hazards 325 Exceptions 333 Parallelism via Instructions 340 Putting it All Together: The Intel Core i7 6700 and ARM Cortex-A53 354 vii
viil Contents Ш Ü! 4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply 363 4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 365 4.15 Fallacies and Pitfalls 365 4.16 Concluding Remarks 367 4.17 Historical Perspective and Further Reading 368 4.18 Self-Study 368 4.19 Exercises 369 Large and Fast: Exploiting Memory Hierarchy 386 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 Introduction 388 Memory Technologies 392 The Basics of Caches 398 Measuring and Improving Cache Performance 412 Dependable Memory Hierarchy 431 Virtual Machines 436 Virtual Memory 440 A Common Framework for Memory Hierarchy 464 Using a Finite-State Machine to Control a Simple Cache 470 Parallelism and Memory Hierarchy: Cache Coherence 475 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks 479 Advanced Material: Implementing Cache Controllers 480 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies 480 Real Stuff: The Rest of the RISC-V System and Special Instructions 486 Going Faster: Cache Blocking and Matrix Multiply 488 Fallacies and Pitfalls 489 Concluding Remarks 494 Historical Perspective and Further Reading 495 Self-Study 495 Exercises 499 Parallel Processors from Client to Cloud 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 518 Introduction 520 The Difficulty of Creating Parallel Processing Programs 522 SISD, MIMD, SIMD, SPMD, and Vector 527 Hardware Multithreading 534 Multicore and Other Shared Memory
Multiprocessors 537 Introduction to Graphics Processing Units 542 Domain-Specific Architectures 549 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors 552
Contents 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 Introduction to Multiprocessor Network Topologies 557 Communicating to the Outside World: Cluster Networking 561 Multiprocessor Benchmarks and Performance Models 561 Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster 572 Going Faster: Multiple Processors and Matrix Multiply 580 Fallacies and Pitfalls 583 Concluding Remarks 585 Historical Perspective and Further Reading 587 Self-Study 588 Exercises 590 APPENDIX The Basics of Logic Design A-2 A.l A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A. 10 A.ll A. 12 A.13 A.14 Index Introduction A-3 Gates, Truth Tables, and Logic Equations A-4 Combinational Logic A-9 Using a Hardware Description Language A-20 Constructing a Basic Arithmetic Logic Unit A-26 Faster Addition: Carry Lookahead A-37 Clocks A-47 Memory Elements: Flip-Flops, Latches, and Registers Memory Elements: SRAMs and DRAMs A-57 Finite-State Machines A-66 Timing Methodologies A-71 Field Programmable Devices A-77 Concluding Remarks A-78 Exercises A-79 1-1 ONLINE CONTENT Graphics and Computing GPUs B-2 B.l B.2 B.3 B.4 B.5 B.6 Introduction B-3 GPU System Architectures B-7 Programming GPUs B-12 Multithreaded Multiprocessor Architecture Paral·lel Memory System B-36 Floating-point Arithmetic B-41 B-25 A-49 ix
x Contents B.7 B.8 B.9 B.10 B.ll Real Stuff: The NVIDIA GeForce 8800 B-46 Real Stuff: Mapping Applications to GPUs B-55 Fallacies and Pitfalls B-72 Concluding Remarks B-76 Historical Perspective and Further Reading B-77 Mapping Control to Hardware C-2 C.l C.2 C.3 C.4 C.5 C.6 C.7 Introduction C-3 Implementing Combinational Control Units C-4 Implementing Finite-State Machine Control C-8 Implementing the Next-State Function with a Sequencer Translating a Microprogram to Hardware C-28 Concluding Remarks C-32 Exercises C-33 Survey of Instruction Set Architectures D.l D.2 C-22 D-2 Introduction D-3 A Survey of RISC Architectures for Desktop, Server, and Embedded Computers D-4 D.3 The Intel 80x86 D-30 D.4 The VAX Architecture D-50 D.5 The IBM 360/370 Architecture for Mainframe Computers D-68 D.6 Historical Perspective and References D-74 Glossary G-l Further Reading FR-1 |
| adam_txt |
Contents Preface xi CHAPTERS Computer Abstractions and Technology 2 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 Introduction 3 Seven Great Ideas in Computer Architecture 10 Below Your Program 13 Under the Covers 16 Technologies for Building Processors and Memory 25 Performance 29 The Power Wall 40 The Sea Change: The Switch from Uniprocessors to Multiprocessors Real Stuff: Benchmarking the Intel Core І7 46 Going Faster: Matrix Multiply in Python 49 Fallacies and Pitfalls 50 Concluding Remarks 53 Historical Perspective and Further Reading 55 Self-Study 55 Exercises 59 Instructions: Language of the Computer 66 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Introduction 68 Operations of the Computer Hardware 69 Operands of the Computer Hardware 73 Signed and Unsigned Numbers 80 Representing Instructions in the Computer 87 Logical Operations 95 Instructions for Making Decisions 98 Supporting Procedures in Computer Hardware 104 Communicating with People 114 RISC-V Addressing for Wide Immediates and Addresses Parallelism and Instructions: Synchronization 128 Translating and Starting a Program 131 AC Sort Example to Put it Ah Together 140 120
Contents 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.26 Arrays versus Pointers 148 Advanced Material: Compiling C and Interpreting Java 151 Real Stuff: MIPS Instructions 152 Real Stuff: ARMv7 (32-bit) Instructions 153 Real Stuff ARMv8 (64-bit) Instructions 157 Real Stuff: x86 Instructions 158 Real Stuff: The Rest of the RISC-V Instruction Set 167 Going Faster: Matrix Multiply in C 168 Fallacies and Pitfalls 170 Concluding Remarks 172 Historical Perspective and Further Reading 174 Self-Study 175 Exercises 178 Arithmetic for Computers 188 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 Introduction 190 Addition and Subtraction 190 Multiplication 193 Division 199 Floating Point 208 Parallelism and Computer Arithmetic: Subword Parallelism 233 Real Stuff Streaming SĪMD Extensions and Advanced Vector Extensions in x86 234 Going Faster: Subword Parallelism and Matrix Multiply 236 Fallacies and Pitfalls 238 Concluding Remarks 241 Historical Perspective and Further Reading 242 Self-Study 242 Exercises 246 The Processor 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 252 Introduction 254 Logic Design Conventions 258 Building a Datapath 261 A Simple Implementation Scheme 269 Multicyle Implementation 282 An Overview of Pipelining 283 Pipelined Datapath and Control 296 Data Hazards: Forwarding versus Stalling 313 Control Hazards 325 Exceptions 333 Parallelism via Instructions 340 Putting it All Together: The Intel Core i7 6700 and ARM Cortex-A53 354 vii
viil Contents Ш Ü! 4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply 363 4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 365 4.15 Fallacies and Pitfalls 365 4.16 Concluding Remarks 367 4.17 Historical Perspective and Further Reading 368 4.18 Self-Study 368 4.19 Exercises 369 Large and Fast: Exploiting Memory Hierarchy 386 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 Introduction 388 Memory Technologies 392 The Basics of Caches 398 Measuring and Improving Cache Performance 412 Dependable Memory Hierarchy 431 Virtual Machines 436 Virtual Memory 440 A Common Framework for Memory Hierarchy 464 Using a Finite-State Machine to Control a Simple Cache 470 Parallelism and Memory Hierarchy: Cache Coherence 475 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks 479 Advanced Material: Implementing Cache Controllers 480 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies 480 Real Stuff: The Rest of the RISC-V System and Special Instructions 486 Going Faster: Cache Blocking and Matrix Multiply 488 Fallacies and Pitfalls 489 Concluding Remarks 494 Historical Perspective and Further Reading 495 Self-Study 495 Exercises 499 Parallel Processors from Client to Cloud 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 518 Introduction 520 The Difficulty of Creating Parallel Processing Programs 522 SISD, MIMD, SIMD, SPMD, and Vector 527 Hardware Multithreading 534 Multicore and Other Shared Memory
Multiprocessors 537 Introduction to Graphics Processing Units 542 Domain-Specific Architectures 549 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors 552
Contents 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 Introduction to Multiprocessor Network Topologies 557 Communicating to the Outside World: Cluster Networking 561 Multiprocessor Benchmarks and Performance Models 561 Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster 572 Going Faster: Multiple Processors and Matrix Multiply 580 Fallacies and Pitfalls 583 Concluding Remarks 585 Historical Perspective and Further Reading 587 Self-Study 588 Exercises 590 APPENDIX The Basics of Logic Design A-2 A.l A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A. 10 A.ll A. 12 A.13 A.14 Index Introduction A-3 Gates, Truth Tables, and Logic Equations A-4 Combinational Logic A-9 Using a Hardware Description Language A-20 Constructing a Basic Arithmetic Logic Unit A-26 Faster Addition: Carry Lookahead A-37 Clocks A-47 Memory Elements: Flip-Flops, Latches, and Registers Memory Elements: SRAMs and DRAMs A-57 Finite-State Machines A-66 Timing Methodologies A-71 Field Programmable Devices A-77 Concluding Remarks A-78 Exercises A-79 1-1 ONLINE CONTENT Graphics and Computing GPUs B-2 B.l B.2 B.3 B.4 B.5 B.6 Introduction B-3 GPU System Architectures B-7 Programming GPUs B-12 Multithreaded Multiprocessor Architecture Paral·lel Memory System B-36 Floating-point Arithmetic B-41 B-25 A-49 ix
x Contents B.7 B.8 B.9 B.10 B.ll Real Stuff: The NVIDIA GeForce 8800 B-46 Real Stuff: Mapping Applications to GPUs B-55 Fallacies and Pitfalls B-72 Concluding Remarks B-76 Historical Perspective and Further Reading B-77 Mapping Control to Hardware C-2 C.l C.2 C.3 C.4 C.5 C.6 C.7 Introduction C-3 Implementing Combinational Control Units C-4 Implementing Finite-State Machine Control C-8 Implementing the Next-State Function with a Sequencer Translating a Microprogram to Hardware C-28 Concluding Remarks C-32 Exercises C-33 Survey of Instruction Set Architectures D.l D.2 C-22 D-2 Introduction D-3 A Survey of RISC Architectures for Desktop, Server, and Embedded Computers D-4 D.3 The Intel 80x86 D-30 D.4 The VAX Architecture D-50 D.5 The IBM 360/370 Architecture for Mainframe Computers D-68 D.6 Historical Perspective and References D-74 Glossary G-l Further Reading FR-1 |
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| title | Computer organization and design the hardware software interface |
| title_auth | Computer organization and design the hardware software interface |
| title_exact_search | Computer organization and design the hardware software interface |
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| title_full | Computer organization and design the hardware software interface David A. Patterson, John L. Hennessy |
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