Networks on Chip:
As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. T...
Gespeichert in:
| Weitere Verfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Springer US
2003
|
| Ausgabe: | 1st ed. 2003 |
| Schlagworte: | |
| Online-Zugang: | UBY01 Volltext |
| Zusammenfassung: | As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation |
| Beschreibung: | 1 Online-Ressource (VIII, 303 p) |
| ISBN: | 9780306487279 |
| DOI: | 10.1007/b105353 |
Internformat
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| 520 | |a As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation | ||
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Datensatz im Suchindex
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| author2 | Jantsch, Axel Tenhunen, Hannu |
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| dewey-full | 003.3 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 003 - Systems |
| dewey-raw | 003.3 |
| dewey-search | 003.3 |
| dewey-sort | 13.3 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| discipline_str_mv | Informatik |
| doi_str_mv | 10.1007/b105353 |
| edition | 1st ed. 2003 |
| format | Electronic eBook |
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| id | DE-604.BV047064484 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T16:12:22Z |
| indexdate | 2024-07-10T09:01:35Z |
| institution | BVB |
| isbn | 9780306487279 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032471596 |
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| physical | 1 Online-Ressource (VIII, 303 p) |
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| spelling | Networks on Chip edited by Axel Jantsch, Hannu Tenhunen 1st ed. 2003 New York, NY Springer US 2003 1 Online-Ressource (VIII, 303 p) txt rdacontent c rdamedia cr rdacarrier As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation Computer System Implementation Processor Architectures Computer-Aided Engineering (CAD, CAE) and Design Operating Systems Special Purpose and Application-Based Systems Architecture, Computer Microprocessors Computer-aided engineering Operating systems (Computers) Special purpose computers Chip (DE-588)4197163-2 gnd rswk-swf Netzwerk (DE-588)4171529-9 gnd rswk-swf Netzwerk (DE-588)4171529-9 s Chip (DE-588)4197163-2 s DE-604 Jantsch, Axel edt Tenhunen, Hannu edt Erscheint auch als Druck-Ausgabe 9781441953445 Erscheint auch als Druck-Ausgabe 9781402073922 Erscheint auch als Druck-Ausgabe 9781475785098 https://doi.org/10.1007/b105353 Verlag URL des Eerstveröffentlichers Volltext |
| spellingShingle | Networks on Chip Computer System Implementation Processor Architectures Computer-Aided Engineering (CAD, CAE) and Design Operating Systems Special Purpose and Application-Based Systems Architecture, Computer Microprocessors Computer-aided engineering Operating systems (Computers) Special purpose computers Chip (DE-588)4197163-2 gnd Netzwerk (DE-588)4171529-9 gnd |
| subject_GND | (DE-588)4197163-2 (DE-588)4171529-9 |
| title | Networks on Chip |
| title_auth | Networks on Chip |
| title_exact_search | Networks on Chip |
| title_exact_search_txtP | Networks on Chip |
| title_full | Networks on Chip edited by Axel Jantsch, Hannu Tenhunen |
| title_fullStr | Networks on Chip edited by Axel Jantsch, Hannu Tenhunen |
| title_full_unstemmed | Networks on Chip edited by Axel Jantsch, Hannu Tenhunen |
| title_short | Networks on Chip |
| title_sort | networks on chip |
| topic | Computer System Implementation Processor Architectures Computer-Aided Engineering (CAD, CAE) and Design Operating Systems Special Purpose and Application-Based Systems Architecture, Computer Microprocessors Computer-aided engineering Operating systems (Computers) Special purpose computers Chip (DE-588)4197163-2 gnd Netzwerk (DE-588)4171529-9 gnd |
| topic_facet | Computer System Implementation Processor Architectures Computer-Aided Engineering (CAD, CAE) and Design Operating Systems Special Purpose and Application-Based Systems Architecture, Computer Microprocessors Computer-aided engineering Operating systems (Computers) Special purpose computers Chip Netzwerk |
| url | https://doi.org/10.1007/b105353 |
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