Logic Synthesis and SOC Prototyping: RTL Design using VHDL
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Bibliographic Details
Main Author: Taraate, Vaibbhav (Author)
Format: Electronic eBook
Language:English
Published: Singapore Springer Singapore 2020
Singapore Springer
Edition:1st ed. 2020
Subjects:
Online Access:BTU01
FAB01
FAW01
FHA01
FHD01
FHI01
FHM01
FHN01
FHR01
FKE01
FLA01
FRO01
FWS01
FWS02
HTW01
TUM01
UBY01
Volltext
Buchcover
Physical Description:1 Online-Ressource (XIX, 251 p)
ISBN:9789811513145
DOI:10.1007/978-981-15-1314-5