APA (7th ed.) Citation

Taraate, V. (2020). Logic Synthesis and SOC Prototyping: RTL Design using VHDL (1st ed. 2020.). Springer Singapore. https://doi.org/10.1007/978-981-15-1314-5

Chicago Style (17th ed.) Citation

Taraate, Vaibbhav. Logic Synthesis and SOC Prototyping: RTL Design Using VHDL. 1st ed. 2020. Singapore: Springer Singapore, 2020. https://doi.org/10.1007/978-981-15-1314-5.

MLA (9th ed.) Citation

Taraate, Vaibbhav. Logic Synthesis and SOC Prototyping: RTL Design Using VHDL. 1st ed. 2020. Springer Singapore, 2020. https://doi.org/10.1007/978-981-15-1314-5.