Innovations in the memory system:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
[San Rafael, California]
Morgan & Claypool Publishers
[2019]
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| Series: | Synthesis lectures on computer architecture
48 |
| Subjects: | |
| Online Access: | Abstract Inhaltsverzeichnis |
| Physical Description: | xxi, 129 Seiten Illustrationen (überwiegend farbig) |
| ISBN: | 9781627056427 9781681736174 |
Staff View
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV046179368 | ||
| 003 | DE-604 | ||
| 005 | 20211007 | ||
| 007 | t | ||
| 008 | 190930s2019 a||| |||| 00||| eng d | ||
| 020 | |a 9781627056427 |9 978-1-62705-642-7 | ||
| 020 | |a 9781681736174 |9 978-1-68173617-4 | ||
| 035 | |a (OCoLC)1143838317 | ||
| 035 | |a (DE-599)BVBBV046179368 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-83 |a DE-11 |a DE-739 | ||
| 084 | |a ZN 5640 |0 (DE-625)157473: |2 rvk | ||
| 084 | |a ST 175 |0 (DE-625)143603: |2 rvk | ||
| 100 | 1 | |a Balasubramonian, Rajeev |e Verfasser |0 (DE-588)1055958142 |4 aut | |
| 245 | 1 | 0 | |a Innovations in the memory system |c Rajeev Balasubramonian, University of Utah |
| 264 | 1 | |a [San Rafael, California] |b Morgan & Claypool Publishers |c [2019] | |
| 264 | 4 | |c © 2019 | |
| 300 | |a xxi, 129 Seiten |b Illustrationen (überwiegend farbig) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Synthesis lectures on computer architecture |v 48 | |
| 490 | 0 | |a Computer & information science |a collection eleven | |
| 490 | 0 | |a Synthesis digital library of engineering and computer science | |
| 650 | 0 | 7 | |a Halbleiterspeicher |0 (DE-588)4120419-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Halbleiterspeicher |0 (DE-588)4120419-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |z 978-1-62705-969-5 |
| 830 | 0 | |a Synthesis lectures on computer architecture |v 48 |w (DE-604)BV023068349 |9 48 | |
| 856 | 4 | 2 | |u https://www.morganclaypool.com/doi/abs/10.2200/S00933ED1V01Y201906CAC048 |x Verlag |3 Abstract |
| 856 | 4 | 2 | |m Digitalisierung UB Passau - ADAM Catalogue Enrichment |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031558932&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-031558932 | ||
Record in the Search Index
| _version_ | 1804180543738216448 |
|---|---|
| adam_text | xi Contents List of Figures............................................................................................................xv List of Tables........................................................................................................... xvii Preface.......................................................................................................................xix Acknowledgments .................................................................................................. xxi 1 Introduction................................................................................................................1 2 Memory System Basics for Every Architect............................................................ 3 3 4 2.1 DRAM vs. SRAM................................................................................................... 3 2.2 Memory Channel.....................................................................................................4 2.3 DDR Standards....................................................................................................... 5 2.4 DIM Ms, Ranks, Banks, Mats................................................................................ 5 2.5 Row Buffers............................................................................................................. 7 2.6 Capacity vs. Energy................................................................................................. 8 2.7 Address Mapping..................................................................................................... 9
2.5 Scheduling................................................................................................................ 9 2.9 DRAM Timing Parameters....................................................................................10 Commercial Memory Products...............................................................................13 3.1 Basic DDR3/DDR4 Channels and DIMMs......................................................13 3.2 DDR Deviations for I ligher Capacity and Bandwidth ..................................... 16 Memory Scheduling.................................................................................................21 4.1 Memory Scheduler Basics............................. 21 4.2 Early Multi-Core Memory Schedulers................................................................22 4.3 Co-Designed Schedulers...................................................................................... 24 4.4 Discussion......................................... 26
xii 5 Data Placement............................................................................................................... 27 5.1 5.2 5.3 6 Memory Chip Microarchitectures ............................................................................. 35 6.1 6.2 6.3 7 7.2 The Basics of Parallel and Serial Interconnects....................................................41 7.1.1 Parallel Buses............................................................................................. 41 7.1.2 Serial Buses............................................................................................... 42 7.1.3 Discussion................................................................................................. 43 Memory Interconnect Innovations...................................................................... 45 7.2.1 Recent Work............................................................................................. 45 7.2.2 Discussion.............................. 49 Memory Reliability .......................................................................................................51 8.1 8.2 8.3 9 Basics of DRAM Chip Microarchitecture .......................................................... 35 DRAM Chip Innovations.....................................................................................37 Discussion............................................................................................................. .40 Memory Channels.........................................................................................................41 7.1
8 Data Interleaving................................................................................................... 27 Memory Compression...........................................................................................28 5.2.1 IBM MXT............................................................................................... 28 5.2.2 Ekman and Stenström ............................................................................ 29 5.2.3 Linearly Compressed Pages (LCP)........................................................29 5.2.4 Nearly Overhead-Free Memory Compression ..................................... 30 5.2.5 PTMC ..................................................................................................... 32 5.2.6 Active Memory Expansion in the IBMPower Processors .................... 32 Discussion................................................................................................................33 Basics of DRAM Errors......................................................................................... 51 Memory Reliability Innovations...........................................................................54 Discussion................................................................................................................58 Memory Refresh............................................................................................................. 59 9.1 9.2 9.3 Refresh Basics..........................................................................................................59 Refresh
Innovations............................................................................................... 63 9.2.1 Empirical Studies and Retention Times................................................63 9.2.2 Alternative Hardware Techniques.......................................................... 65 9.2.3 Alternative Software Techniques............................................................ 66 9.2.4 Leveraging Charge in Cells.................................................................... 66 Discussion................................................................................................................67
xiii 10 11 12 Near Data Processing...............................................................................................69 10.1 NDP Implementations...........................................................................................70 10.1.1 3D Stacked Architectures........................................................................ 70 10.1.2 Tight Coupling on a DIMM..................................................................71 10.2 10.3 In-Situ Implementations.......................................................................................73 Programming Models and Applications..............................................................77 10.3.1 Programming Approaches ...................................................................... 77 10.3.2 Broadening the Scope of NDP with Additional Workloads.............. 79 10.4 Discussion............................................................................................................... 80 Memory Security..................................................................................................... 81 11.1 11.2 11.3 11.4 11.5 Memory Timing Channels.................................................................................. 81 Oblivious RAM (ORAM)......................... 87 M e m o ry I n tegri ty...................................................................................................91 I mpact of Smart Memories.................................................................................. 98 Other Memory Security Issues
........................................................................... 99 11.6 Discussion............................................................................................................. 100 Closing Thoughts............................................................. 103 Bibliography........................................................................................................... 105 Authors Biography................................................................................................. 129
|
| any_adam_object | 1 |
| author | Balasubramonian, Rajeev |
| author_GND | (DE-588)1055958142 |
| author_facet | Balasubramonian, Rajeev |
| author_role | aut |
| author_sort | Balasubramonian, Rajeev |
| author_variant | r b rb |
| building | Verbundindex |
| bvnumber | BV046179368 |
| classification_rvk | ZN 5640 ST 175 |
| ctrlnum | (OCoLC)1143838317 (DE-599)BVBBV046179368 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01905nam a2200421 cb4500</leader><controlfield tag="001">BV046179368</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20211007 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">190930s2019 a||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781627056427</subfield><subfield code="9">978-1-62705-642-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781681736174</subfield><subfield code="9">978-1-68173617-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1143838317</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV046179368</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-83</subfield><subfield code="a">DE-11</subfield><subfield code="a">DE-739</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5640</subfield><subfield code="0">(DE-625)157473:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 175</subfield><subfield code="0">(DE-625)143603:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Balasubramonian, Rajeev</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)1055958142</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Innovations in the memory system</subfield><subfield code="c">Rajeev Balasubramonian, University of Utah</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">[San Rafael, California]</subfield><subfield code="b">Morgan & Claypool Publishers</subfield><subfield code="c">[2019]</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">© 2019</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">xxi, 129 Seiten</subfield><subfield code="b">Illustrationen (überwiegend farbig)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Synthesis lectures on computer architecture</subfield><subfield code="v">48</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Computer & information science</subfield><subfield code="a">collection eleven</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Synthesis digital library of engineering and computer science</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Halbleiterspeicher</subfield><subfield code="0">(DE-588)4120419-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Halbleiterspeicher</subfield><subfield code="0">(DE-588)4120419-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Online-Ausgabe</subfield><subfield code="z">978-1-62705-969-5</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Synthesis lectures on computer architecture</subfield><subfield code="v">48</subfield><subfield code="w">(DE-604)BV023068349</subfield><subfield code="9">48</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://www.morganclaypool.com/doi/abs/10.2200/S00933ED1V01Y201906CAC048</subfield><subfield code="x">Verlag</subfield><subfield code="3">Abstract</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung UB Passau - ADAM Catalogue Enrichment</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031558932&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-031558932</subfield></datafield></record></collection> |
| id | DE-604.BV046179368 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:37:26Z |
| institution | BVB |
| isbn | 9781627056427 9781681736174 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-031558932 |
| oclc_num | 1143838317 |
| open_access_boolean | |
| owner | DE-83 DE-11 DE-739 |
| owner_facet | DE-83 DE-11 DE-739 |
| physical | xxi, 129 Seiten Illustrationen (überwiegend farbig) |
| publishDate | 2019 |
| publishDateSearch | 2019 |
| publishDateSort | 2019 |
| publisher | Morgan & Claypool Publishers |
| record_format | marc |
| series | Synthesis lectures on computer architecture |
| series2 | Synthesis lectures on computer architecture Computer & information science collection eleven Synthesis digital library of engineering and computer science |
| spelling | Balasubramonian, Rajeev Verfasser (DE-588)1055958142 aut Innovations in the memory system Rajeev Balasubramonian, University of Utah [San Rafael, California] Morgan & Claypool Publishers [2019] © 2019 xxi, 129 Seiten Illustrationen (überwiegend farbig) txt rdacontent n rdamedia nc rdacarrier Synthesis lectures on computer architecture 48 Computer & information science collection eleven Synthesis digital library of engineering and computer science Halbleiterspeicher (DE-588)4120419-0 gnd rswk-swf Halbleiterspeicher (DE-588)4120419-0 s DE-604 Erscheint auch als Online-Ausgabe 978-1-62705-969-5 Synthesis lectures on computer architecture 48 (DE-604)BV023068349 48 https://www.morganclaypool.com/doi/abs/10.2200/S00933ED1V01Y201906CAC048 Verlag Abstract Digitalisierung UB Passau - ADAM Catalogue Enrichment application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031558932&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Balasubramonian, Rajeev Innovations in the memory system Synthesis lectures on computer architecture Halbleiterspeicher (DE-588)4120419-0 gnd |
| subject_GND | (DE-588)4120419-0 |
| title | Innovations in the memory system |
| title_auth | Innovations in the memory system |
| title_exact_search | Innovations in the memory system |
| title_full | Innovations in the memory system Rajeev Balasubramonian, University of Utah |
| title_fullStr | Innovations in the memory system Rajeev Balasubramonian, University of Utah |
| title_full_unstemmed | Innovations in the memory system Rajeev Balasubramonian, University of Utah |
| title_short | Innovations in the memory system |
| title_sort | innovations in the memory system |
| topic | Halbleiterspeicher (DE-588)4120419-0 gnd |
| topic_facet | Halbleiterspeicher |
| url | https://www.morganclaypool.com/doi/abs/10.2200/S00933ED1V01Y201906CAC048 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031558932&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV023068349 |
| work_keys_str_mv | AT balasubramonianrajeev innovationsinthememorysystem |