Innovations in the memory system:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
[San Rafael, California]
Morgan & Claypool Publishers
[2019]
|
| Schriftenreihe: | Synthesis lectures on computer architecture
48 |
| Schlagworte: | |
| Online-Zugang: | Abstract Inhaltsverzeichnis |
| Beschreibung: | xxi, 129 Seiten Illustrationen (überwiegend farbig) |
| ISBN: | 9781627056427 9781681736174 |
Internformat
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Datensatz im Suchindex
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|---|---|
| adam_text | xi Contents List of Figures............................................................................................................xv List of Tables........................................................................................................... xvii Preface.......................................................................................................................xix Acknowledgments .................................................................................................. xxi 1 Introduction................................................................................................................1 2 Memory System Basics for Every Architect............................................................ 3 3 4 2.1 DRAM vs. SRAM................................................................................................... 3 2.2 Memory Channel.....................................................................................................4 2.3 DDR Standards....................................................................................................... 5 2.4 DIM Ms, Ranks, Banks, Mats................................................................................ 5 2.5 Row Buffers............................................................................................................. 7 2.6 Capacity vs. Energy................................................................................................. 8 2.7 Address Mapping..................................................................................................... 9
2.5 Scheduling................................................................................................................ 9 2.9 DRAM Timing Parameters....................................................................................10 Commercial Memory Products...............................................................................13 3.1 Basic DDR3/DDR4 Channels and DIMMs......................................................13 3.2 DDR Deviations for I ligher Capacity and Bandwidth ..................................... 16 Memory Scheduling.................................................................................................21 4.1 Memory Scheduler Basics............................. 21 4.2 Early Multi-Core Memory Schedulers................................................................22 4.3 Co-Designed Schedulers...................................................................................... 24 4.4 Discussion......................................... 26
xii 5 Data Placement............................................................................................................... 27 5.1 5.2 5.3 6 Memory Chip Microarchitectures ............................................................................. 35 6.1 6.2 6.3 7 7.2 The Basics of Parallel and Serial Interconnects....................................................41 7.1.1 Parallel Buses............................................................................................. 41 7.1.2 Serial Buses............................................................................................... 42 7.1.3 Discussion................................................................................................. 43 Memory Interconnect Innovations...................................................................... 45 7.2.1 Recent Work............................................................................................. 45 7.2.2 Discussion.............................. 49 Memory Reliability .......................................................................................................51 8.1 8.2 8.3 9 Basics of DRAM Chip Microarchitecture .......................................................... 35 DRAM Chip Innovations.....................................................................................37 Discussion............................................................................................................. .40 Memory Channels.........................................................................................................41 7.1
8 Data Interleaving................................................................................................... 27 Memory Compression...........................................................................................28 5.2.1 IBM MXT............................................................................................... 28 5.2.2 Ekman and Stenström ............................................................................ 29 5.2.3 Linearly Compressed Pages (LCP)........................................................29 5.2.4 Nearly Overhead-Free Memory Compression ..................................... 30 5.2.5 PTMC ..................................................................................................... 32 5.2.6 Active Memory Expansion in the IBMPower Processors .................... 32 Discussion................................................................................................................33 Basics of DRAM Errors......................................................................................... 51 Memory Reliability Innovations...........................................................................54 Discussion................................................................................................................58 Memory Refresh............................................................................................................. 59 9.1 9.2 9.3 Refresh Basics..........................................................................................................59 Refresh
Innovations............................................................................................... 63 9.2.1 Empirical Studies and Retention Times................................................63 9.2.2 Alternative Hardware Techniques.......................................................... 65 9.2.3 Alternative Software Techniques............................................................ 66 9.2.4 Leveraging Charge in Cells.................................................................... 66 Discussion................................................................................................................67
xiii 10 11 12 Near Data Processing...............................................................................................69 10.1 NDP Implementations...........................................................................................70 10.1.1 3D Stacked Architectures........................................................................ 70 10.1.2 Tight Coupling on a DIMM..................................................................71 10.2 10.3 In-Situ Implementations.......................................................................................73 Programming Models and Applications..............................................................77 10.3.1 Programming Approaches ...................................................................... 77 10.3.2 Broadening the Scope of NDP with Additional Workloads.............. 79 10.4 Discussion............................................................................................................... 80 Memory Security..................................................................................................... 81 11.1 11.2 11.3 11.4 11.5 Memory Timing Channels.................................................................................. 81 Oblivious RAM (ORAM)......................... 87 M e m o ry I n tegri ty...................................................................................................91 I mpact of Smart Memories.................................................................................. 98 Other Memory Security Issues
........................................................................... 99 11.6 Discussion............................................................................................................. 100 Closing Thoughts............................................................. 103 Bibliography........................................................................................................... 105 Authors Biography................................................................................................. 129
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| spelling | Balasubramonian, Rajeev Verfasser (DE-588)1055958142 aut Innovations in the memory system Rajeev Balasubramonian, University of Utah [San Rafael, California] Morgan & Claypool Publishers [2019] © 2019 xxi, 129 Seiten Illustrationen (überwiegend farbig) txt rdacontent n rdamedia nc rdacarrier Synthesis lectures on computer architecture 48 Computer & information science collection eleven Synthesis digital library of engineering and computer science Halbleiterspeicher (DE-588)4120419-0 gnd rswk-swf Halbleiterspeicher (DE-588)4120419-0 s DE-604 Erscheint auch als Online-Ausgabe 978-1-62705-969-5 Synthesis lectures on computer architecture 48 (DE-604)BV023068349 48 https://www.morganclaypool.com/doi/abs/10.2200/S00933ED1V01Y201906CAC048 Verlag Abstract Digitalisierung UB Passau - ADAM Catalogue Enrichment application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031558932&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Balasubramonian, Rajeev Innovations in the memory system Synthesis lectures on computer architecture Halbleiterspeicher (DE-588)4120419-0 gnd |
| subject_GND | (DE-588)4120419-0 |
| title | Innovations in the memory system |
| title_auth | Innovations in the memory system |
| title_exact_search | Innovations in the memory system |
| title_full | Innovations in the memory system Rajeev Balasubramonian, University of Utah |
| title_fullStr | Innovations in the memory system Rajeev Balasubramonian, University of Utah |
| title_full_unstemmed | Innovations in the memory system Rajeev Balasubramonian, University of Utah |
| title_short | Innovations in the memory system |
| title_sort | innovations in the memory system |
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